| Message ID | 1665637711-13300-1-git-send-email-quic_srivasam@quicinc.com |
|---|---|
| State | Accepted |
| Commit | c9a3545b1d771fb7b06a487796c40288c02c41c5 |
| Headers | show |
| Series | [v2] ASoC: qcom: lpass-cpu: mark HDMI TX registers as volatile | expand |
Quoting Srinivasa Rao Mandadapu (2022-10-12 22:08:31) > Update HDMI volatile registers list as DMA, Channel Selection registers, > vbit control registers are being reflected by hardware DP port > disconnection. > > This update is required to fix no display and no sound issue observed > after reconnecting TAMA/SANWA DP cables. > Once DP cable is unplugged, DMA control registers are being reset by > hardware, however at second plugin, new dma control values does not > updated to the dma hardware registers since new register value and > cached values at the time of first plugin are same. > > Fixes: 7cb37b7bd0d3 ("ASoC: qcom: Add support for lpass hdmi driver") > > Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> > Reported-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- I found that another patch in this area hasn't been applied[1]. Is it still relevant? We're still carrying it in the chromium tree. If it is relevant can you please resend it. [1] https://lore.kernel.org/all/1602596728-11783-1-git-send-email-srivasam@codeaurora.org/
On 10/15/2022 2:41 AM, Stephen Boyd wrote: > Quoting Srinivasa Rao Mandadapu (2022-10-12 22:08:31) >> Update HDMI volatile registers list as DMA, Channel Selection registers, >> vbit control registers are being reflected by hardware DP port >> disconnection. >> >> This update is required to fix no display and no sound issue observed >> after reconnecting TAMA/SANWA DP cables. >> Once DP cable is unplugged, DMA control registers are being reset by >> hardware, however at second plugin, new dma control values does not >> updated to the dma hardware registers since new register value and >> cached values at the time of first plugin are same. >> >> Fixes: 7cb37b7bd0d3 ("ASoC: qcom: Add support for lpass hdmi driver") >> >> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> >> Reported-by: Kuogee Hsieh <quic_khsieh@quicinc.com> >> --- > I found that another patch in this area hasn't been applied[1]. Is it > still relevant? We're still carrying it in the chromium tree. If it is > relevant can you please resend it. > > [1] https://lore.kernel.org/all/1602596728-11783-1-git-send-email-srivasam@codeaurora.org/ Thanks for Notifying this untracked patch. Resent the patch. - https://patchwork.kernel.org/project/alsa-devel/patch/1665825530-7593-1-git-send-email-quic_srivasam@quicinc.com/
diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c index 8a56f38..99a3b44 100644 --- a/sound/soc/qcom/lpass-cpu.c +++ b/sound/soc/qcom/lpass-cpu.c @@ -782,10 +782,18 @@ static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg) return true; if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v)) return true; + if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v)) + return true; for (i = 0; i < v->hdmi_rdma_channels; ++i) { if (reg == LPAIF_HDMI_RDMACURR_REG(v, i)) return true; + if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i)) + return true; + if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i)) + return true; + if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i)) + return true; } return false; }
Update HDMI volatile registers list as DMA, Channel Selection registers, vbit control registers are being reflected by hardware DP port disconnection. This update is required to fix no display and no sound issue observed after reconnecting TAMA/SANWA DP cables. Once DP cable is unplugged, DMA control registers are being reset by hardware, however at second plugin, new dma control values does not updated to the dma hardware registers since new register value and cached values at the time of first plugin are same. Fixes: 7cb37b7bd0d3 ("ASoC: qcom: Add support for lpass hdmi driver") Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Reported-by: Kuogee Hsieh <quic_khsieh@quicinc.com> --- sound/soc/qcom/lpass-cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+)