| Message ID | 20221019110647.11076-17-victor.shih@genesyslogic.com.tw |
|---|---|
| State | New |
| Headers | show |
| Series | Add support UHS-II for GL9755 | expand |
On 19/10/22 14:06, Victor Shih wrote: > Sdhci_uhs2_do_detect_init() is a sdhci version of mmc's uhs2_detect_init > operation. After detected, the host's UHS-II capabilities will be set up > here and interrupts will also be enabled. > > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> > Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> > Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw> > --- > drivers/mmc/host/sdhci-uhs2.c | 146 ++++++++++++++++++++++++++++++++++ > 1 file changed, 146 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c > index b535a47dc55a..9ceae552c323 100644 > --- a/drivers/mmc/host/sdhci-uhs2.c > +++ b/drivers/mmc/host/sdhci-uhs2.c > @@ -409,12 +409,158 @@ int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) > * * > \*****************************************************************************/ > > +static int sdhci_uhs2_interface_detect(struct sdhci_host *host) > +{ > + /* 100ms */ > + int timeout = 100000; > + u32 val; > + > + udelay(200); /* wait for 200us before check */ > + > + if (read_poll_timeout_atomic(sdhci_readl, val, (val & SDHCI_UHS2_IF_DETECT), > + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { > + pr_warn("%s: not detect UHS2 interface in 200us.\n", mmc_hostname(host->mmc)); > + sdhci_dumpregs(host); > + return -EIO; > + } > + > + /* Enable UHS2 error interrupts */ > + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, > + SDHCI_UHS2_ERR_INT_STATUS_MASK); > + > + /* 150ms */ > + timeout = 150000; > + if (read_poll_timeout_atomic(sdhci_readl, val, (val & SDHCI_UHS2_LANE_SYNC), > + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { > + pr_warn("%s: UHS2 Lane sync fail in 150ms.\n", mmc_hostname(host->mmc)); > + sdhci_dumpregs(host); > + return -EIO; > + } > + > + DBG("%s: UHS2 Lane synchronized in UHS2 mode, PHY is initialized.\n", > + mmc_hostname(host->mmc)); > + return 0; > +} > + > +static int sdhci_uhs2_init(struct sdhci_host *host) > +{ > + u16 caps_ptr = 0; > + u32 caps_gen = 0; > + u32 caps_phy = 0; > + u32 caps_tran[2] = {0, 0}; > + struct mmc_host *mmc = host->mmc; > + > + caps_ptr = sdhci_readw(host, SDHCI_UHS2_HOST_CAPS_PTR); > + if (caps_ptr < 0x100 || caps_ptr > 0x1FF) { > + pr_err("%s: SDHCI_UHS2_HOST_CAPS_PTR(%d) is wrong.\n", > + mmc_hostname(mmc), caps_ptr); > + return -ENODEV; > + } > + caps_gen = sdhci_readl(host, > + caps_ptr + SDHCI_UHS2_HOST_CAPS_GEN_OFFSET); Please wrap at 100 columns not 80, here and elsewhere. > + caps_phy = sdhci_readl(host, > + caps_ptr + SDHCI_UHS2_HOST_CAPS_PHY_OFFSET); > + caps_tran[0] = sdhci_readl(host, > + caps_ptr + SDHCI_UHS2_HOST_CAPS_TRAN_OFFSET); > + caps_tran[1] = sdhci_readl(host, > + caps_ptr > + + SDHCI_UHS2_HOST_CAPS_TRAN_1_OFFSET); > + > + /* General Caps */ > + mmc->uhs2_caps.dap = caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_DAP_MASK; > + mmc->uhs2_caps.gap = (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_GAP_MASK) >> > + SDHCI_UHS2_HOST_CAPS_GEN_GAP_SHIFT; > + mmc->uhs2_caps.n_lanes = (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_LANE_MASK) > + >> SDHCI_UHS2_HOST_CAPS_GEN_LANE_SHIFT; > + mmc->uhs2_caps.addr64 = > + (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_ADDR_64) ? 1 : 0; > + mmc->uhs2_caps.card_type = > + (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_DEV_TYPE_MASK) >> > + SDHCI_UHS2_HOST_CAPS_GEN_DEV_TYPE_SHIFT; > + > + /* PHY Caps */ > + mmc->uhs2_caps.phy_rev = caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_REV_MASK; > + mmc->uhs2_caps.speed_range = > + (caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_RANGE_MASK) > + >> SDHCI_UHS2_HOST_CAPS_PHY_RANGE_SHIFT; > + mmc->uhs2_caps.n_lss_sync = > + (caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_SYN_MASK) > + >> SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_SYN_SHIFT; > + mmc->uhs2_caps.n_lss_dir = > + (caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_DIR_MASK) > + >> SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_DIR_SHIFT; > + if (mmc->uhs2_caps.n_lss_sync == 0) > + mmc->uhs2_caps.n_lss_sync = 16 << 2; > + else > + mmc->uhs2_caps.n_lss_sync <<= 2; > + if (mmc->uhs2_caps.n_lss_dir == 0) > + mmc->uhs2_caps.n_lss_dir = 16 << 3; > + else > + mmc->uhs2_caps.n_lss_dir <<= 3; > + > + /* LINK/TRAN Caps */ > + mmc->uhs2_caps.link_rev = > + caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_LINK_REV_MASK; > + mmc->uhs2_caps.n_fcu = > + (caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_N_FCU_MASK) > + >> SDHCI_UHS2_HOST_CAPS_TRAN_N_FCU_SHIFT; > + if (mmc->uhs2_caps.n_fcu == 0) > + mmc->uhs2_caps.n_fcu = 256; > + mmc->uhs2_caps.host_type = > + (caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_HOST_TYPE_MASK) > + >> SDHCI_UHS2_HOST_CAPS_TRAN_HOST_TYPE_SHIFT; > + mmc->uhs2_caps.maxblk_len = > + (caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_BLK_LEN_MASK) > + >> SDHCI_UHS2_HOST_CAPS_TRAN_BLK_LEN_SHIFT; > + mmc->uhs2_caps.n_data_gap = > + caps_tran[1] & SDHCI_UHS2_HOST_CAPS_TRAN_1_N_DATA_GAP_MASK; > + > + return 0; > +} > + > +static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc) > +{ > + struct sdhci_host *host = mmc_priv(mmc); > + int ret = -EIO; > + > + DBG("%s: begin UHS2 init.\n", __func__); > + > + if (sdhci_uhs2_interface_detect(host)) { > + pr_warn("%s: cannot detect UHS2 interface.\n", > + mmc_hostname(host->mmc)); > + goto out; > + } > + > + if (sdhci_uhs2_init(host)) { > + pr_warn("%s: UHS2 init fail.\n", mmc_hostname(host->mmc)); > + goto out; > + } > + > + /* Init complete, do soft reset and enable UHS2 error irqs. */ > + host->ops->uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); > + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, > + SDHCI_UHS2_ERR_INT_STATUS_MASK); > + /* > + * !!! SDHCI_INT_ENABLE and SDHCI_SIGNAL_ENABLE was cleared !!! is a little dramatic, what about just N.B. > + * by SDHCI_UHS2_SW_RESET_SD > + */ > + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); > + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); > + > + ret = 0; > +out: > + return ret; > +} > + > static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) > { > host->mmc_host_ops.start_signal_voltage_switch = > sdhci_uhs2_start_signal_voltage_switch; > host->mmc_host_ops.uhs2_set_ios = sdhci_uhs2_set_ios; > > + if (!host->mmc_host_ops.uhs2_detect_init) > + host->mmc_host_ops.uhs2_detect_init = sdhci_uhs2_do_detect_init; As mentioned before ->uhs2_detect_init() is never called. > + > return 0; > } >
Hi, Adrian On Wed, Nov 2, 2022 at 1:14 AM Adrian Hunter <adrian.hunter@intel.com> wrote: > > On 19/10/22 14:06, Victor Shih wrote: > > Sdhci_uhs2_do_detect_init() is a sdhci version of mmc's uhs2_detect_init > > operation. After detected, the host's UHS-II capabilities will be set up > > here and interrupts will also be enabled. > > > > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> > > Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> > > Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw> > > --- > > drivers/mmc/host/sdhci-uhs2.c | 146 ++++++++++++++++++++++++++++++++++ > > 1 file changed, 146 insertions(+) > > > > diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c > > index b535a47dc55a..9ceae552c323 100644 > > --- a/drivers/mmc/host/sdhci-uhs2.c > > +++ b/drivers/mmc/host/sdhci-uhs2.c > > @@ -409,12 +409,158 @@ int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) > > * * > > \*****************************************************************************/ > > > > +static int sdhci_uhs2_interface_detect(struct sdhci_host *host) > > +{ > > + /* 100ms */ > > + int timeout = 100000; > > + u32 val; > > + > > + udelay(200); /* wait for 200us before check */ > > + > > + if (read_poll_timeout_atomic(sdhci_readl, val, (val & SDHCI_UHS2_IF_DETECT), > > + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { > > + pr_warn("%s: not detect UHS2 interface in 200us.\n", mmc_hostname(host->mmc)); > > + sdhci_dumpregs(host); > > + return -EIO; > > + } > > + > > + /* Enable UHS2 error interrupts */ > > + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, > > + SDHCI_UHS2_ERR_INT_STATUS_MASK); > > + > > + /* 150ms */ > > + timeout = 150000; > > + if (read_poll_timeout_atomic(sdhci_readl, val, (val & SDHCI_UHS2_LANE_SYNC), > > + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { > > + pr_warn("%s: UHS2 Lane sync fail in 150ms.\n", mmc_hostname(host->mmc)); > > + sdhci_dumpregs(host); > > + return -EIO; > > + } > > + > > + DBG("%s: UHS2 Lane synchronized in UHS2 mode, PHY is initialized.\n", > > + mmc_hostname(host->mmc)); > > + return 0; > > +} > > + > > +static int sdhci_uhs2_init(struct sdhci_host *host) > > +{ > > + u16 caps_ptr = 0; > > + u32 caps_gen = 0; > > + u32 caps_phy = 0; > > + u32 caps_tran[2] = {0, 0}; > > + struct mmc_host *mmc = host->mmc; > > + > > + caps_ptr = sdhci_readw(host, SDHCI_UHS2_HOST_CAPS_PTR); > > + if (caps_ptr < 0x100 || caps_ptr > 0x1FF) { > > + pr_err("%s: SDHCI_UHS2_HOST_CAPS_PTR(%d) is wrong.\n", > > + mmc_hostname(mmc), caps_ptr); > > + return -ENODEV; > > + } > > + caps_gen = sdhci_readl(host, > > + caps_ptr + SDHCI_UHS2_HOST_CAPS_GEN_OFFSET); > > Please wrap at 100 columns not 80, here and elsewhere. > I will update it in the patch#15 of the new [PATCH V6]. > > + caps_phy = sdhci_readl(host, > > + caps_ptr + SDHCI_UHS2_HOST_CAPS_PHY_OFFSET); > > + caps_tran[0] = sdhci_readl(host, > > + caps_ptr + SDHCI_UHS2_HOST_CAPS_TRAN_OFFSET); > > + caps_tran[1] = sdhci_readl(host, > > + caps_ptr > > + + SDHCI_UHS2_HOST_CAPS_TRAN_1_OFFSET); > > + > > + /* General Caps */ > > + mmc->uhs2_caps.dap = caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_DAP_MASK; > > + mmc->uhs2_caps.gap = (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_GAP_MASK) >> > > + SDHCI_UHS2_HOST_CAPS_GEN_GAP_SHIFT; > > + mmc->uhs2_caps.n_lanes = (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_LANE_MASK) > > + >> SDHCI_UHS2_HOST_CAPS_GEN_LANE_SHIFT; > > + mmc->uhs2_caps.addr64 = > > + (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_ADDR_64) ? 1 : 0; > > + mmc->uhs2_caps.card_type = > > + (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_DEV_TYPE_MASK) >> > > + SDHCI_UHS2_HOST_CAPS_GEN_DEV_TYPE_SHIFT; > > + > > + /* PHY Caps */ > > + mmc->uhs2_caps.phy_rev = caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_REV_MASK; > > + mmc->uhs2_caps.speed_range = > > + (caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_RANGE_MASK) > > + >> SDHCI_UHS2_HOST_CAPS_PHY_RANGE_SHIFT; > > + mmc->uhs2_caps.n_lss_sync = > > + (caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_SYN_MASK) > > + >> SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_SYN_SHIFT; > > + mmc->uhs2_caps.n_lss_dir = > > + (caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_DIR_MASK) > > + >> SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_DIR_SHIFT; > > + if (mmc->uhs2_caps.n_lss_sync == 0) > > + mmc->uhs2_caps.n_lss_sync = 16 << 2; > > + else > > + mmc->uhs2_caps.n_lss_sync <<= 2; > > + if (mmc->uhs2_caps.n_lss_dir == 0) > > + mmc->uhs2_caps.n_lss_dir = 16 << 3; > > + else > > + mmc->uhs2_caps.n_lss_dir <<= 3; > > + > > + /* LINK/TRAN Caps */ > > + mmc->uhs2_caps.link_rev = > > + caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_LINK_REV_MASK; > > + mmc->uhs2_caps.n_fcu = > > + (caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_N_FCU_MASK) > > + >> SDHCI_UHS2_HOST_CAPS_TRAN_N_FCU_SHIFT; > > + if (mmc->uhs2_caps.n_fcu == 0) > > + mmc->uhs2_caps.n_fcu = 256; > > + mmc->uhs2_caps.host_type = > > + (caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_HOST_TYPE_MASK) > > + >> SDHCI_UHS2_HOST_CAPS_TRAN_HOST_TYPE_SHIFT; > > + mmc->uhs2_caps.maxblk_len = > > + (caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_BLK_LEN_MASK) > > + >> SDHCI_UHS2_HOST_CAPS_TRAN_BLK_LEN_SHIFT; > > + mmc->uhs2_caps.n_data_gap = > > + caps_tran[1] & SDHCI_UHS2_HOST_CAPS_TRAN_1_N_DATA_GAP_MASK; > > + > > + return 0; > > +} > > + > > +static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc) > > +{ > > + struct sdhci_host *host = mmc_priv(mmc); > > + int ret = -EIO; > > + > > + DBG("%s: begin UHS2 init.\n", __func__); > > + > > + if (sdhci_uhs2_interface_detect(host)) { > > + pr_warn("%s: cannot detect UHS2 interface.\n", > > + mmc_hostname(host->mmc)); > > + goto out; > > + } > > + > > + if (sdhci_uhs2_init(host)) { > > + pr_warn("%s: UHS2 init fail.\n", mmc_hostname(host->mmc)); > > + goto out; > > + } > > + > > + /* Init complete, do soft reset and enable UHS2 error irqs. */ > > + host->ops->uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); > > + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, > > + SDHCI_UHS2_ERR_INT_STATUS_MASK); > > + /* > > + * !!! SDHCI_INT_ENABLE and SDHCI_SIGNAL_ENABLE was cleared > > !!! is a little dramatic, what about just N.B. > I will update it in the patch#15 of the new [PATCH V6]. > > + * by SDHCI_UHS2_SW_RESET_SD > > + */ > > + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); > > + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); > > + > > + ret = 0; > > +out: > > + return ret; > > +} > > + > > static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) > > { > > host->mmc_host_ops.start_signal_voltage_switch = > > sdhci_uhs2_start_signal_voltage_switch; > > host->mmc_host_ops.uhs2_set_ios = sdhci_uhs2_set_ios; > > > > + if (!host->mmc_host_ops.uhs2_detect_init) > > + host->mmc_host_ops.uhs2_detect_init = sdhci_uhs2_do_detect_init; > > As mentioned before ->uhs2_detect_init() is never called. > > > + > > return 0; > > } > > > Thanks, Victor Shih
diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index b535a47dc55a..9ceae552c323 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -409,12 +409,158 @@ int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) * * \*****************************************************************************/ +static int sdhci_uhs2_interface_detect(struct sdhci_host *host) +{ + /* 100ms */ + int timeout = 100000; + u32 val; + + udelay(200); /* wait for 200us before check */ + + if (read_poll_timeout_atomic(sdhci_readl, val, (val & SDHCI_UHS2_IF_DETECT), + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { + pr_warn("%s: not detect UHS2 interface in 200us.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + + /* Enable UHS2 error interrupts */ + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, + SDHCI_UHS2_ERR_INT_STATUS_MASK); + + /* 150ms */ + timeout = 150000; + if (read_poll_timeout_atomic(sdhci_readl, val, (val & SDHCI_UHS2_LANE_SYNC), + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { + pr_warn("%s: UHS2 Lane sync fail in 150ms.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + + DBG("%s: UHS2 Lane synchronized in UHS2 mode, PHY is initialized.\n", + mmc_hostname(host->mmc)); + return 0; +} + +static int sdhci_uhs2_init(struct sdhci_host *host) +{ + u16 caps_ptr = 0; + u32 caps_gen = 0; + u32 caps_phy = 0; + u32 caps_tran[2] = {0, 0}; + struct mmc_host *mmc = host->mmc; + + caps_ptr = sdhci_readw(host, SDHCI_UHS2_HOST_CAPS_PTR); + if (caps_ptr < 0x100 || caps_ptr > 0x1FF) { + pr_err("%s: SDHCI_UHS2_HOST_CAPS_PTR(%d) is wrong.\n", + mmc_hostname(mmc), caps_ptr); + return -ENODEV; + } + caps_gen = sdhci_readl(host, + caps_ptr + SDHCI_UHS2_HOST_CAPS_GEN_OFFSET); + caps_phy = sdhci_readl(host, + caps_ptr + SDHCI_UHS2_HOST_CAPS_PHY_OFFSET); + caps_tran[0] = sdhci_readl(host, + caps_ptr + SDHCI_UHS2_HOST_CAPS_TRAN_OFFSET); + caps_tran[1] = sdhci_readl(host, + caps_ptr + + SDHCI_UHS2_HOST_CAPS_TRAN_1_OFFSET); + + /* General Caps */ + mmc->uhs2_caps.dap = caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_DAP_MASK; + mmc->uhs2_caps.gap = (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_GAP_MASK) >> + SDHCI_UHS2_HOST_CAPS_GEN_GAP_SHIFT; + mmc->uhs2_caps.n_lanes = (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_LANE_MASK) + >> SDHCI_UHS2_HOST_CAPS_GEN_LANE_SHIFT; + mmc->uhs2_caps.addr64 = + (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_ADDR_64) ? 1 : 0; + mmc->uhs2_caps.card_type = + (caps_gen & SDHCI_UHS2_HOST_CAPS_GEN_DEV_TYPE_MASK) >> + SDHCI_UHS2_HOST_CAPS_GEN_DEV_TYPE_SHIFT; + + /* PHY Caps */ + mmc->uhs2_caps.phy_rev = caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_REV_MASK; + mmc->uhs2_caps.speed_range = + (caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_RANGE_MASK) + >> SDHCI_UHS2_HOST_CAPS_PHY_RANGE_SHIFT; + mmc->uhs2_caps.n_lss_sync = + (caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_SYN_MASK) + >> SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_SYN_SHIFT; + mmc->uhs2_caps.n_lss_dir = + (caps_phy & SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_DIR_MASK) + >> SDHCI_UHS2_HOST_CAPS_PHY_N_LSS_DIR_SHIFT; + if (mmc->uhs2_caps.n_lss_sync == 0) + mmc->uhs2_caps.n_lss_sync = 16 << 2; + else + mmc->uhs2_caps.n_lss_sync <<= 2; + if (mmc->uhs2_caps.n_lss_dir == 0) + mmc->uhs2_caps.n_lss_dir = 16 << 3; + else + mmc->uhs2_caps.n_lss_dir <<= 3; + + /* LINK/TRAN Caps */ + mmc->uhs2_caps.link_rev = + caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_LINK_REV_MASK; + mmc->uhs2_caps.n_fcu = + (caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_N_FCU_MASK) + >> SDHCI_UHS2_HOST_CAPS_TRAN_N_FCU_SHIFT; + if (mmc->uhs2_caps.n_fcu == 0) + mmc->uhs2_caps.n_fcu = 256; + mmc->uhs2_caps.host_type = + (caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_HOST_TYPE_MASK) + >> SDHCI_UHS2_HOST_CAPS_TRAN_HOST_TYPE_SHIFT; + mmc->uhs2_caps.maxblk_len = + (caps_tran[0] & SDHCI_UHS2_HOST_CAPS_TRAN_BLK_LEN_MASK) + >> SDHCI_UHS2_HOST_CAPS_TRAN_BLK_LEN_SHIFT; + mmc->uhs2_caps.n_data_gap = + caps_tran[1] & SDHCI_UHS2_HOST_CAPS_TRAN_1_N_DATA_GAP_MASK; + + return 0; +} + +static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + int ret = -EIO; + + DBG("%s: begin UHS2 init.\n", __func__); + + if (sdhci_uhs2_interface_detect(host)) { + pr_warn("%s: cannot detect UHS2 interface.\n", + mmc_hostname(host->mmc)); + goto out; + } + + if (sdhci_uhs2_init(host)) { + pr_warn("%s: UHS2 init fail.\n", mmc_hostname(host->mmc)); + goto out; + } + + /* Init complete, do soft reset and enable UHS2 error irqs. */ + host->ops->uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, + SDHCI_UHS2_ERR_INT_STATUS_MASK); + /* + * !!! SDHCI_INT_ENABLE and SDHCI_SIGNAL_ENABLE was cleared + * by SDHCI_UHS2_SW_RESET_SD + */ + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + + ret = 0; +out: + return ret; +} + static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) { host->mmc_host_ops.start_signal_voltage_switch = sdhci_uhs2_start_signal_voltage_switch; host->mmc_host_ops.uhs2_set_ios = sdhci_uhs2_set_ios; + if (!host->mmc_host_ops.uhs2_detect_init) + host->mmc_host_ops.uhs2_detect_init = sdhci_uhs2_do_detect_init; + return 0; }