diff mbox series

[01/20] arm64: dts: Update cache properties for amd

Message ID 20221031091903.531009-1-pierre.gondois@arm.com
State New
Headers show
Series [01/20] arm64: dts: Update cache properties for amd | expand

Commit Message

Pierre Gondois Oct. 31, 2022, 9:19 a.m. UTC 
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes

The recently added init_of_cache_level() function checks
these properties. Add them if missing.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
 arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
index 93688a0b6820..9f2d983e082d 100644
--- a/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
+++ b/arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
@@ -163,38 +163,47 @@  CPU7: cpu@301 {
 	};
 
 	L2_0: l2-cache0 {
+		compatible = "cache";
 		cache-size = <0x100000>;
 		cache-line-size = <64>;
 		cache-sets = <1024>;
 		cache-unified;
+		cache-level = <2>;
 		next-level-cache = <&L3>;
 	};
 
 	L2_1: l2-cache1 {
+		compatible = "cache";
 		cache-size = <0x100000>;
 		cache-line-size = <64>;
 		cache-sets = <1024>;
 		cache-unified;
+		cache-level = <2>;
 		next-level-cache = <&L3>;
 	};
 
 	L2_2: l2-cache2 {
+		compatible = "cache";
 		cache-size = <0x100000>;
 		cache-line-size = <64>;
 		cache-sets = <1024>;
 		cache-unified;
+		cache-level = <2>;
 		next-level-cache = <&L3>;
 	};
 
 	L2_3: l2-cache3 {
+		compatible = "cache";
 		cache-size = <0x100000>;
 		cache-line-size = <64>;
 		cache-sets = <1024>;
 		cache-unified;
+		cache-level = <2>;
 		next-level-cache = <&L3>;
 	};
 
 	L3: l3-cache {
+		compatible = "cache";
 		cache-level = <3>;
 		cache-size = <0x800000>;
 		cache-line-size = <64>;