| Message ID | 20221107005433.11079-4-andre.przywara@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | None | expand |
Dne ponedeljek, 07. november 2022 ob 01:54:26 CET je Andre Przywara napisal(a): > The Allwinner F1C100s series of SoCs contain three I2C controllers > compatible to the ones used in other Allwinner SoCs. > > Add the DT nodes describing the resources of the controllers. > I2C1 has only one possible pinmux, so add the pinctrl properties for > that already. Above statement doesn't match current changes anymore. With that removed: Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> If nothing else pops up, I can fix this while applying. Best regards, Jernej > At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so > include those pins already, to simplify referencing them later. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > arch/arm/boot/dts/suniv-f1c100s.dtsi | 42 ++++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi > b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 81749d5da12f..4f45168cea42 > 100644 > --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi > +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi > @@ -192,6 +192,12 @@ mmc0_pins: mmc0-pins { > drive-strength = <30>; > }; > > + /omit-if-no-ref/ > + i2c0_pd_pins: i2c0-pd-pins { > + pins = "PD0", "PD12"; > + function = "i2c0"; > + }; > + > spi0_pc_pins: spi0-pc-pins { > pins = "PC0", "PC1", "PC2", "PC3"; > function = "spi0"; > @@ -203,6 +209,42 @@ uart0_pe_pins: uart0-pe-pins { > }; > }; > > + i2c0: i2c@1c27000 { > + compatible = "allwinner,suniv-f1c100s-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x01c27000 0x400>; > + interrupts = <7>; > + clocks = <&ccu CLK_BUS_I2C0>; > + resets = <&ccu RST_BUS_I2C0>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c1: i2c@1c27400 { > + compatible = "allwinner,suniv-f1c100s-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x01c27400 0x400>; > + interrupts = <8>; > + clocks = <&ccu CLK_BUS_I2C1>; > + resets = <&ccu RST_BUS_I2C1>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c2: i2c@1c27800 { > + compatible = "allwinner,suniv-f1c100s-i2c", > + "allwinner,sun6i-a31-i2c"; > + reg = <0x01c27800 0x400>; > + interrupts = <9>; > + clocks = <&ccu CLK_BUS_I2C2>; > + resets = <&ccu RST_BUS_I2C2>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > timer@1c20c00 { > compatible = "allwinner,suniv-f1c100s- timer"; > reg = <0x01c20c00 0x90>; > -- > 2.35.5
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 81749d5da12f..4f45168cea42 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -192,6 +192,12 @@ mmc0_pins: mmc0-pins { drive-strength = <30>; }; + /omit-if-no-ref/ + i2c0_pd_pins: i2c0-pd-pins { + pins = "PD0", "PD12"; + function = "i2c0"; + }; + spi0_pc_pins: spi0-pc-pins { pins = "PC0", "PC1", "PC2", "PC3"; function = "spi0"; @@ -203,6 +209,42 @@ uart0_pe_pins: uart0-pe-pins { }; }; + i2c0: i2c@1c27000 { + compatible = "allwinner,suniv-f1c100s-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c27000 0x400>; + interrupts = <7>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@1c27400 { + compatible = "allwinner,suniv-f1c100s-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c27400 0x400>; + interrupts = <8>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@1c27800 { + compatible = "allwinner,suniv-f1c100s-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c27800 0x400>; + interrupts = <9>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + timer@1c20c00 { compatible = "allwinner,suniv-f1c100s-timer"; reg = <0x01c20c00 0x90>;
The Allwinner F1C100s series of SoCs contain three I2C controllers compatible to the ones used in other Allwinner SoCs. Add the DT nodes describing the resources of the controllers. I2C1 has only one possible pinmux, so add the pinctrl properties for that already. At least one board connects an on-board I2C chip to PD0/PD12 (I2C0), so include those pins already, to simplify referencing them later. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)