Message ID | 20221111182535.64844-17-alex.bennee@linaro.org |
---|---|
State | New |
Headers | show
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Fri, 11 Nov 2022 10:25:39 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 47B061FFC6; Fri, 11 Nov 2022 18:25:37 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org> To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org> Subject: [PATCH v5 16/20] include: add MEMTXATTRS_MACHINE helper Date: Fri, 11 Nov 2022 18:25:31 +0000 Message-Id: <20221111182535.64844-17-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org |
Series |
use MemTxAttrs to avoid current_cpu in hw/
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expand
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On 11/12/22 04:25, Alex Bennée wrote: > We will need this shortly for machine specific transactions for the PC > IOAPIC. > > Signed-off-by: Alex Bennée<alex.bennee@linaro.org> > --- > include/exec/memattrs.h | 8 ++++++++ > 1 file changed, 8 insertions(+) Fold into patch 1? Anyway, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 8359fc448b..b92f11aaa4 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -104,6 +104,14 @@ typedef struct MemTxAttrs { {.requester_type = MTRT_PCI, \ .requester_id = pci_requester_id(dev)}) +/* + * Helper for setting a machine specific sourced transaction. The + * details of how to decode the requester_id are machine specific. + */ +#define MEMTXATTRS_MACHINE(id) ((MemTxAttrs) \ + {.requester_type = MTRT_MACHINE, \ + .requester_id = id }) + /* New-style MMIO accessors can indicate that the transaction failed. * A zero (MEMTX_OK) response means success; anything else is a failure * of some kind. The memory subsystem will bitwise-OR together results
We will need this shortly for machine specific transactions for the PC IOAPIC. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> --- include/exec/memattrs.h | 8 ++++++++ 1 file changed, 8 insertions(+)