| Message ID | 20221115154637.1613968-1-robdclark@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v3] drm/msm/a6xx: Fix speed-bin detection vs probe-defer | expand |
On 11/15/2022 9:16 PM, Rob Clark wrote: > From: Rob Clark <robdclark@chromium.org> > > If we get an error (other than -ENOENT) we need to propagate that up the > stack. Otherwise if the nvmem driver hasn't probed yet, we'll end up > end up claiming that we support all the OPPs which is not likely to be > true (and on some generations impossible to be true, ie. if there are > conflicting OPPs). > > v2: Update commit msg, gc unused label, etc > v3: Add previously missing \n's > > Fixed: fe7952c629da ("drm/msm: Add speed-bin support to a618 gpu") > Signed-off-by: Rob Clark <robdclark@chromium.org> > Reviewed-by: Douglas Anderson <dianders@chromium.org> > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++------- > 1 file changed, 5 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 7fe60c65a1eb..ebe9599a8316 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1931,7 +1931,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) > > if (val == UINT_MAX) { > DRM_DEV_ERROR(dev, > - "missing support for speed-bin: %u. Some OPPs may not be supported by hardware", > + "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", > fuse); > return UINT_MAX; > } > @@ -1941,7 +1941,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) > > static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) > { > - u32 supp_hw = UINT_MAX; > + u32 supp_hw; > u32 speedbin; > int ret; > > @@ -1953,15 +1953,13 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) > if (ret == -ENOENT) { > return 0; > } else if (ret) { > - DRM_DEV_ERROR(dev, > - "failed to read speed-bin (%d). Some OPPs may not be supported by hardware", > - ret); > - goto done; > + dev_err_probe(dev, ret, > + "failed to read speed-bin. Some OPPs may not be supported by hardware\n"); > + return ret; > } > > supp_hw = fuse_to_supp_hw(dev, rev, speedbin); > > -done: > ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); > if (ret) > return ret; Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> -Akhil.
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 7fe60c65a1eb..ebe9599a8316 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1931,7 +1931,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) if (val == UINT_MAX) { DRM_DEV_ERROR(dev, - "missing support for speed-bin: %u. Some OPPs may not be supported by hardware", + "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", fuse); return UINT_MAX; } @@ -1941,7 +1941,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) { - u32 supp_hw = UINT_MAX; + u32 supp_hw; u32 speedbin; int ret; @@ -1953,15 +1953,13 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) if (ret == -ENOENT) { return 0; } else if (ret) { - DRM_DEV_ERROR(dev, - "failed to read speed-bin (%d). Some OPPs may not be supported by hardware", - ret); - goto done; + dev_err_probe(dev, ret, + "failed to read speed-bin. Some OPPs may not be supported by hardware\n"); + return ret; } supp_hw = fuse_to_supp_hw(dev, rev, speedbin); -done: ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); if (ret) return ret;