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[2/6] dt-bindings: i2c: qcom-geni: document I2C Master Hub serial I2C engine

Message ID 20221114-narmstrong-sm8550-upstream-i2c-master-hub-v1-2-64449106a148@linaro.org
State New
Headers show
Series soc: qcom: add support for the I2C Master Hub | expand

Commit Message

Neil Armstrong Nov. 16, 2022, 10:21 a.m. UTC
The I2C Master Hub is a stripped down version of the GENI Serial Engine
QUP Wrapper Controller but only supporting I2C serial engines without
DMA support.

This documents the I2C Serial Engine variant used within the I2C Master
Hub Wrapper. This serial engine variant lacks DMA support, and requires
a core clock, and since DMA support is lacking, the memory interconnect
path isn't needed.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 .../bindings/i2c/qcom,i2c-geni-qcom.yaml           | 61 +++++++++++++++++-----
 1 file changed, 49 insertions(+), 12 deletions(-)
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Patch

diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
index 0e7ed00562e2..ea2c28e70cf5 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
@@ -15,13 +15,13 @@  allOf:
 
 properties:
   compatible:
-    const: qcom,geni-i2c
+    enum:
+      - qcom,geni-i2c
+      - qcom,geni-i2c-master-hub
 
-  clocks:
-    maxItems: 1
+  clocks: true
 
-  clock-names:
-    const: se
+  clock-names: true
 
   clock-frequency:
     default: 100000
@@ -34,14 +34,9 @@  properties:
       - const: tx
       - const: rx
 
-  interconnects:
-    maxItems: 3
+  interconnects: true
 
-  interconnect-names:
-    items:
-      - const: qup-core
-      - const: qup-config
-      - const: qup-memory
+  interconnect-names: true
 
   interrupts:
     maxItems: 1
@@ -71,6 +66,48 @@  required:
   - clock-names
   - reg
 
+if:
+  properties:
+    compatible:
+      contains:
+        const: qcom,geni-i2c-master-hub
+then:
+  properties:
+    clock-names:
+      items:
+        - const: se
+        - const: core
+
+    clocks:
+      maxItems: 2
+
+    dmas: false
+    dma-names: false
+
+    interconnects:
+      maxItems: 2
+
+    interconnect-names:
+      items:
+        - const: qup-core
+        - const: qup-config
+else:
+  properties:
+    clocks:
+      maxItems: 1
+
+    clock-names:
+      const: se
+
+    interconnects:
+      maxItems: 3
+
+    interconnect-names:
+      items:
+        - const: qup-core
+        - const: qup-config
+        - const: qup-memory
+
 unevaluatedProperties: false
 
 examples: