| Message ID | 20221124115023.2437291-3-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Convert most CPU classes to 3-phase reset | expand |
On 11/24/22 12:50, Peter Maydell wrote: > Convert the Arm CPU class to use 3-phase reset, so it doesn't > need to use device_class_set_parent_reset() any more. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > target/arm/cpu-qom.h | 4 ++-- > target/arm/cpu.c | 13 +++++++++---- > 2 files changed, 11 insertions(+), 6 deletions(-) > > diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h > index 64c44cef2dd..514c22ced9b 100644 > --- a/target/arm/cpu-qom.h > +++ b/target/arm/cpu-qom.h > @@ -43,7 +43,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info); > /** > * ARMCPUClass: > * @parent_realize: The parent class' realize handler. > - * @parent_reset: The parent class' reset handler. > + * @parent_phases: The parent class' reset phase handlers. > * > * An ARM CPU model. > */ > @@ -54,7 +54,7 @@ struct ARMCPUClass { > > const ARMCPUInfo *info; > DeviceRealize parent_realize; > - DeviceReset parent_reset; > + ResettablePhases parent_phases; > }; > > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index a021df9e9e8..5bad065579f 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -202,14 +202,16 @@ static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) > assert(oldvalue == newvalue); > } > > -static void arm_cpu_reset(DeviceState *dev) > +static void arm_cpu_reset_hold(Object *obj) > { > - CPUState *s = CPU(dev); > + CPUState *s = CPU(obj); > ARMCPU *cpu = ARM_CPU(s); > ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); > CPUARMState *env = &cpu->env; > > - acc->parent_reset(dev); > + if (acc->parent_phases.hold) { > + acc->parent_phases.hold(obj); > + } > > memset(env, 0, offsetof(CPUARMState, end_reset_fields)); > > @@ -2210,12 +2212,15 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) > ARMCPUClass *acc = ARM_CPU_CLASS(oc); > CPUClass *cc = CPU_CLASS(acc); > DeviceClass *dc = DEVICE_CLASS(oc); > + ResettableClass *rc = RESETTABLE_CLASS(oc); > > device_class_set_parent_realize(dc, arm_cpu_realizefn, > &acc->parent_realize); > > device_class_set_props(dc, arm_cpu_properties); > - device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); > + > + resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, > + &acc->parent_phases); > > cc->class_by_name = arm_cpu_class_by_name; > cc->has_work = arm_cpu_has_work;
On Thu, Nov 24, 2022 at 9:58 PM Peter Maydell <peter.maydell@linaro.org> wrote: > > Convert the Arm CPU class to use 3-phase reset, so it doesn't > need to use device_class_set_parent_reset() any more. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/arm/cpu-qom.h | 4 ++-- > target/arm/cpu.c | 13 +++++++++---- > 2 files changed, 11 insertions(+), 6 deletions(-) > > diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h > index 64c44cef2dd..514c22ced9b 100644 > --- a/target/arm/cpu-qom.h > +++ b/target/arm/cpu-qom.h > @@ -43,7 +43,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info); > /** > * ARMCPUClass: > * @parent_realize: The parent class' realize handler. > - * @parent_reset: The parent class' reset handler. > + * @parent_phases: The parent class' reset phase handlers. > * > * An ARM CPU model. > */ > @@ -54,7 +54,7 @@ struct ARMCPUClass { > > const ARMCPUInfo *info; > DeviceRealize parent_realize; > - DeviceReset parent_reset; > + ResettablePhases parent_phases; > }; > > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index a021df9e9e8..5bad065579f 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -202,14 +202,16 @@ static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) > assert(oldvalue == newvalue); > } > > -static void arm_cpu_reset(DeviceState *dev) > +static void arm_cpu_reset_hold(Object *obj) > { > - CPUState *s = CPU(dev); > + CPUState *s = CPU(obj); > ARMCPU *cpu = ARM_CPU(s); > ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); > CPUARMState *env = &cpu->env; > > - acc->parent_reset(dev); > + if (acc->parent_phases.hold) { > + acc->parent_phases.hold(obj); > + } > > memset(env, 0, offsetof(CPUARMState, end_reset_fields)); > > @@ -2210,12 +2212,15 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) > ARMCPUClass *acc = ARM_CPU_CLASS(oc); > CPUClass *cc = CPU_CLASS(acc); > DeviceClass *dc = DEVICE_CLASS(oc); > + ResettableClass *rc = RESETTABLE_CLASS(oc); > > device_class_set_parent_realize(dc, arm_cpu_realizefn, > &acc->parent_realize); > > device_class_set_props(dc, arm_cpu_properties); > - device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); > + > + resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, > + &acc->parent_phases); > > cc->class_by_name = arm_cpu_class_by_name; > cc->has_work = arm_cpu_has_work; > -- > 2.25.1 > >
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 64c44cef2dd..514c22ced9b 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -43,7 +43,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info); /** * ARMCPUClass: * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. + * @parent_phases: The parent class' reset phase handlers. * * An ARM CPU model. */ @@ -54,7 +54,7 @@ struct ARMCPUClass { const ARMCPUInfo *info; DeviceRealize parent_realize; - DeviceReset parent_reset; + ResettablePhases parent_phases; }; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a021df9e9e8..5bad065579f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -202,14 +202,16 @@ static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) assert(oldvalue == newvalue); } -static void arm_cpu_reset(DeviceState *dev) +static void arm_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(dev); + CPUState *s = CPU(obj); ARMCPU *cpu = ARM_CPU(s); ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); CPUARMState *env = &cpu->env; - acc->parent_reset(dev); + if (acc->parent_phases.hold) { + acc->parent_phases.hold(obj); + } memset(env, 0, offsetof(CPUARMState, end_reset_fields)); @@ -2210,12 +2212,15 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) ARMCPUClass *acc = ARM_CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(acc); DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); device_class_set_parent_realize(dc, arm_cpu_realizefn, &acc->parent_realize); device_class_set_props(dc, arm_cpu_properties); - device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset); + + resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL, + &acc->parent_phases); cc->class_by_name = arm_cpu_class_by_name; cc->has_work = arm_cpu_has_work;
Convert the Arm CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu-qom.h | 4 ++-- target/arm/cpu.c | 13 +++++++++---- 2 files changed, 11 insertions(+), 6 deletions(-)