| Message ID | 20221124115023.2437291-5-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Convert most CPU classes to 3-phase reset | expand |
On Thu, Nov 24, 2022 at 11:50:07AM +0000, Peter Maydell wrote: > Convert the cris CPU class to use 3-phase reset, so it doesn't > need to use device_class_set_parent_reset() any more. Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/cris/cpu-qom.h | 4 ++-- > target/cris/cpu.c | 12 ++++++++---- > 2 files changed, 10 insertions(+), 6 deletions(-) > > diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h > index 71e8af0e70a..431a1d536a9 100644 > --- a/target/cris/cpu-qom.h > +++ b/target/cris/cpu-qom.h > @@ -30,7 +30,7 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU) > /** > * CRISCPUClass: > * @parent_realize: The parent class' realize handler. > - * @parent_reset: The parent class' reset handler. > + * @parent_phases: The parent class' reset phase handlers. > * @vr: Version Register value. > * > * A CRIS CPU model. > @@ -41,7 +41,7 @@ struct CRISCPUClass { > /*< public >*/ > > DeviceRealize parent_realize; > - DeviceReset parent_reset; > + ResettablePhases parent_phases; > > uint32_t vr; > }; > diff --git a/target/cris/cpu.c b/target/cris/cpu.c > index fb05dc6f9ab..a6a93c23595 100644 > --- a/target/cris/cpu.c > +++ b/target/cris/cpu.c > @@ -56,15 +56,17 @@ static bool cris_cpu_has_work(CPUState *cs) > return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); > } > > -static void cris_cpu_reset(DeviceState *dev) > +static void cris_cpu_reset_hold(Object *obj) > { > - CPUState *s = CPU(dev); > + CPUState *s = CPU(obj); > CRISCPU *cpu = CRIS_CPU(s); > CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); > CPUCRISState *env = &cpu->env; > uint32_t vr; > > - ccc->parent_reset(dev); > + if (ccc->parent_phases.hold) { > + ccc->parent_phases.hold(obj); > + } > > vr = env->pregs[PR_VR]; > memset(env, 0, offsetof(CPUCRISState, end_reset_fields)); > @@ -305,11 +307,13 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) > DeviceClass *dc = DEVICE_CLASS(oc); > CPUClass *cc = CPU_CLASS(oc); > CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); > + ResettableClass *rc = RESETTABLE_CLASS(oc); > > device_class_set_parent_realize(dc, cris_cpu_realizefn, > &ccc->parent_realize); > > - device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset); > + resettable_class_set_parent_phases(rc, NULL, cris_cpu_reset_hold, NULL, > + &ccc->parent_phases); > > cc->class_by_name = cris_cpu_class_by_name; > cc->has_work = cris_cpu_has_work; > -- > 2.25.1 >
diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h index 71e8af0e70a..431a1d536a9 100644 --- a/target/cris/cpu-qom.h +++ b/target/cris/cpu-qom.h @@ -30,7 +30,7 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU) /** * CRISCPUClass: * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. + * @parent_phases: The parent class' reset phase handlers. * @vr: Version Register value. * * A CRIS CPU model. @@ -41,7 +41,7 @@ struct CRISCPUClass { /*< public >*/ DeviceRealize parent_realize; - DeviceReset parent_reset; + ResettablePhases parent_phases; uint32_t vr; }; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index fb05dc6f9ab..a6a93c23595 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -56,15 +56,17 @@ static bool cris_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } -static void cris_cpu_reset(DeviceState *dev) +static void cris_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(dev); + CPUState *s = CPU(obj); CRISCPU *cpu = CRIS_CPU(s); CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); CPUCRISState *env = &cpu->env; uint32_t vr; - ccc->parent_reset(dev); + if (ccc->parent_phases.hold) { + ccc->parent_phases.hold(obj); + } vr = env->pregs[PR_VR]; memset(env, 0, offsetof(CPUCRISState, end_reset_fields)); @@ -305,11 +307,13 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); CPUClass *cc = CPU_CLASS(oc); CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); device_class_set_parent_realize(dc, cris_cpu_realizefn, &ccc->parent_realize); - device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, cris_cpu_reset_hold, NULL, + &ccc->parent_phases); cc->class_by_name = cris_cpu_class_by_name; cc->has_work = cris_cpu_has_work;
Convert the cris CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/cris/cpu-qom.h | 4 ++-- target/cris/cpu.c | 12 ++++++++---- 2 files changed, 10 insertions(+), 6 deletions(-)