| Message ID | 20221212093315.11390-2-konrad.dybcio@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [1/3] dt-bindings: display/msm: Add SM8150 MDSS & DPU | expand |
On Mon, Dec 12, 2022 at 10:33:13AM +0100, Konrad Dybcio wrote: > Years after the SoC support has been added, it's high time for it to > get dispcc going. Add the node to ensure that. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8150.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > index a0c57fb798d3..ff04397777f4 100644 > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > @@ -3579,6 +3579,32 @@ camnoc_virt: interconnect@ac00000 { > qcom,bcm-voters = <&apps_bcm_voter>; > }; > > + dispcc: clock-controller@af00000 { > + compatible = "qcom,sm8150-dispcc"; > + reg = <0 0x0af00000 0 0x10000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>; > + clock-names = "bi_tcxo", > + "dsi0_phy_pll_out_byteclk", > + "dsi0_phy_pll_out_dsiclk", > + "dsi1_phy_pll_out_byteclk", > + "dsi1_phy_pll_out_dsiclk", > + "dp_phy_pll_link_clk", > + "dp_phy_pll_vco_div_clk"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + > + power-domains = <&rpmhpd SM8150_MMCX>; > + /* TODO: Maybe rpmhpd_opp_min_svs could work as well? */ The power-domain being not disabled should be sufficient for us to access the dispcc. Beyond that votes would be needed for particular frequencies, and that goes in the client nodes/opp-tables. So you should be able to drop this comment and the required-opps. Regards, Bjorn > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > pdc: interrupt-controller@b220000 { > compatible = "qcom,sm8150-pdc", "qcom,pdc"; > reg = <0 0x0b220000 0 0x400>; > -- > 2.38.1 >
On 2022-12-27 22:16:58, Bjorn Andersson wrote: > On Mon, Dec 12, 2022 at 10:33:13AM +0100, Konrad Dybcio wrote: > > [..] > > + power-domains = <&rpmhpd SM8150_MMCX>; > > + /* TODO: Maybe rpmhpd_opp_min_svs could work as well? */ > > The power-domain being not disabled should be sufficient for us to > access the dispcc. Beyond that votes would be needed for particular > frequencies, and that goes in the client nodes/opp-tables. > > So you should be able to drop this comment and the required-opps. > > Regards, > Bjorn > > > + required-opps = <&rpmhpd_opp_low_svs>; Tested the removal of this on Xperia 5, no regressions. - Marijn
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a0c57fb798d3..ff04397777f4 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3579,6 +3579,32 @@ camnoc_virt: interconnect@ac00000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8150-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + power-domains = <&rpmhpd SM8150_MMCX>; + /* TODO: Maybe rpmhpd_opp_min_svs could work as well? */ + required-opps = <&rpmhpd_opp_low_svs>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8150-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x400>;
Years after the SoC support has been added, it's high time for it to get dispcc going. Add the node to ensure that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)