| Message ID | 1456952926-10704-1-git-send-email-evan.lloyd@arm.com |
|---|---|
| State | Accepted |
| Commit | ff1f27c055c9dd78eb457bbf8cb7511060e3ee0b |
| Headers | show |
On Wed, Mar 02, 2016 at 09:08:46PM +0000, evan.lloyd@arm.com wrote: > From: Evan Lloyd <evan.lloyd@arm.com> > > Architecturally, the TTBCR register value is undefined at reset for > Non-Secure. > On some platforms the reset value for TTBCR is not zero and > this causes a data abort exception once the MMU is enabled. > > This patch configures the TTBCR register to enable translation table > walk using TTBR0. Thanks Evan, pushed with one hopefully non-contentious modification to your updated comment (see below). > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> > diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c > index fc8ea42..7caff5a 100644 > --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c > +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c > @@ -1,7 +1,7 @@ > /** @file > * File managing the MMU for ARMv7 architecture > * > -* Copyright (c) 2011-2013, ARM Limited. All rights reserved. > +* Copyright (c) 2011-2016, ARM Limited. All rights reserved. > * > * This program and the accompanying materials > * are licensed and made available under the terms and conditions of the BSD License > @@ -347,6 +347,16 @@ ArmConfigureMmu ( > > ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F))); > > + // > + // The TTBCR register value is undefined at reset in the Non-Secure world. > + // Writing 0 has the effect of: > + // Clearing EAE: Use short descriptors, as mandated by specification. > + // Clearing PD0 and PD1: Translation Table Walk Disable is off. > + // Clearing N: Perform all translation table walks through TTBR0. > + // (0 is the default reset value, in non-secure systems.) + // (0 is the default reset value in systems not implementing + // the Security Extensions.) > + // > + ArmSetTTBCR (0); > + > ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) | > DOMAIN_ACCESS_CONTROL_NONE(14) | > DOMAIN_ACCESS_CONTROL_NONE(13) | _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index 85fa1f6..15f610d 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -1,7 +1,7 @@ /** @file Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> - Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License @@ -353,6 +353,12 @@ ArmSetTTBR0 ( IN VOID *TranslationTableBase ); +VOID +EFIAPI +ArmSetTTBCR ( + IN UINT32 Bits + ); + VOID * EFIAPI ArmGetTTBR0BaseAddress ( diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c index fc8ea42..7caff5a 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c @@ -1,7 +1,7 @@ /** @file * File managing the MMU for ARMv7 architecture * -* Copyright (c) 2011-2013, ARM Limited. All rights reserved. +* Copyright (c) 2011-2016, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -347,6 +347,16 @@ ArmConfigureMmu ( ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F))); + // + // The TTBCR register value is undefined at reset in the Non-Secure world. + // Writing 0 has the effect of: + // Clearing EAE: Use short descriptors, as mandated by specification. + // Clearing PD0 and PD1: Translation Table Walk Disable is off. + // Clearing N: Perform all translation table walks through TTBR0. + // (0 is the default reset value, in non-secure systems.) + // + ArmSetTTBCR (0); + ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) | DOMAIN_ACCESS_CONTROL_NONE(14) | DOMAIN_ACCESS_CONTROL_NONE(13) | diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S index 085f08b..5d1194e 100644 --- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.S @@ -1,7 +1,7 @@ #------------------------------------------------------------------------------ # # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> -# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. +# Copyright (c) 2011 - 2016, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -23,6 +23,7 @@ GCC_ASM_EXPORT(ArmGetInterruptState) GCC_ASM_EXPORT(ArmGetFiqState) GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress) GCC_ASM_EXPORT(ArmSetTTBR0) +GCC_ASM_EXPORT(ArmSetTTBCR) GCC_ASM_EXPORT(ArmSetDomainAccessControl) GCC_ASM_EXPORT(CPSRMaskInsert) GCC_ASM_EXPORT(CPSRRead) @@ -111,6 +112,11 @@ ASM_PFX(ArmSetTTBR0): isb bx lr +ASM_PFX(ArmSetTTBCR): + mcr p15, 0, r0, c2, c0, 2 + isb + bx lr + ASM_PFX(ArmGetTTBR0BaseAddress): mrc p15,0,r0,c2,c0,0 LoadConstantToReg(0xFFFFC000, r1) diff --git a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm index 228d7c8..9b87b7f 100644 --- a/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm +++ b/ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm @@ -1,7 +1,7 @@ //------------------------------------------------------------------------------ // // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> -// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. +// Copyright (c) 2011 - 2016, ARM Limited. All rights reserved. // // This program and the accompanying materials // are licensed and made available under the terms and conditions of the BSD License @@ -85,6 +85,11 @@ isb bx lr + RVCT_ASM_EXPORT ArmSetTTBCR + mcr p15, 0, r0, c2, c0, 2 + isb + bx lr + RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress mrc p15,0,r0,c2,c0,0 LoadConstantToReg(0xFFFFC000, r1)