@@ -37,7 +37,7 @@ OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
/**
* Nios2CPUClass:
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
*
* A Nios2 CPU model.
*/
@@ -47,7 +47,7 @@ struct Nios2CPUClass {
/*< public >*/
DeviceRealize parent_realize;
- DeviceReset parent_reset;
+ ResettablePhases parent_phases;
};
#define TARGET_HAS_ICE 1
@@ -57,14 +57,16 @@ static bool nios2_cpu_has_work(CPUState *cs)
return cs->interrupt_request & CPU_INTERRUPT_HARD;
}
-static void nios2_cpu_reset(DeviceState *dev)
+static void nios2_cpu_reset_hold(Object *obj)
{
- CPUState *cs = CPU(dev);
+ CPUState *cs = CPU(obj);
Nios2CPU *cpu = NIOS2_CPU(cs);
Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu);
CPUNios2State *env = &cpu->env;
- ncc->parent_reset(dev);
+ if (ncc->parent_phases.hold) {
+ ncc->parent_phases.hold(obj);
+ }
memset(env->ctrl, 0, sizeof(env->ctrl));
env->pc = cpu->reset_addr;
@@ -371,11 +373,13 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
Nios2CPUClass *ncc = NIOS2_CPU_CLASS(oc);
+ ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, nios2_cpu_realizefn,
&ncc->parent_realize);
device_class_set_props(dc, nios2_properties);
- device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset);
+ resettable_class_set_parent_phases(rc, NULL, nios2_cpu_reset_hold, NULL,
+ &ncc->parent_phases);
cc->class_by_name = nios2_cpu_class_by_name;
cc->has_work = nios2_cpu_has_work;