@@ -356,7 +356,7 @@ OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
/**
* LoongArchCPUClass:
* @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
*
* A LoongArch CPU model.
*/
@@ -366,7 +366,7 @@ struct LoongArchCPUClass {
/*< public >*/
DeviceRealize parent_realize;
- DeviceReset parent_reset;
+ ResettablePhases parent_phases;
};
/*
@@ -450,14 +450,16 @@ void loongarch_cpu_list(void)
g_slist_free(list);
}
-static void loongarch_cpu_reset(DeviceState *dev)
+static void loongarch_cpu_reset_hold(Object *obj)
{
- CPUState *cs = CPU(dev);
+ CPUState *cs = CPU(obj);
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu);
CPULoongArchState *env = &cpu->env;
- lacc->parent_reset(dev);
+ if (lacc->parent_phases.hold) {
+ lacc->parent_phases.hold(obj);
+ }
env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3;
env->fcsr0 = 0x0;
@@ -694,10 +696,12 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c);
+ ResettableClass *rc = RESETTABLE_CLASS(c);
device_class_set_parent_realize(dc, loongarch_cpu_realizefn,
&lacc->parent_realize);
- device_class_set_parent_reset(dc, loongarch_cpu_reset, &lacc->parent_reset);
+ resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL,
+ &lacc->parent_phases);
cc->class_by_name = loongarch_cpu_class_by_name;
cc->has_work = loongarch_cpu_has_work;