diff mbox series

[v2,2/4] dt-bindings: clock: qcom,sc7280-lpasscc: Add resets for audioreach

Message ID 1672407799-13768-3-git-send-email-quic_srivasam@quicinc.com
State New
Headers show
Series Add resets for ADSP based audio clock controller driver. | expand

Commit Message

Srinivasa Rao Mandadapu Dec. 30, 2022, 1:43 p.m. UTC 
Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
for audioreach based SC7280 platforms.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
---
 .../devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml         | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

Comments

Krzysztof Kozlowski Jan. 2, 2023, 4:06 p.m. UTC | #1 
On 30/12/2022 14:43, Srinivasa Rao Mandadapu wrote:
> Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
> for audioreach based SC7280 platforms.
> 
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
> Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
> ---
>  .../devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml         | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
> index 9c72b8e..40fc6ab 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
> @@ -31,13 +31,18 @@ properties:
>    '#clock-cells':
>      const: 1
>  
> +  '#reset-cells':
> +    const: 1
> +
>    reg:
>      items:
>        - description: LPASS top-cc register
> +      - description: LPASS reset-cgcr register

It's now even a bigger mess. First ABI break, then bring it back to
previous stage - so two IO addresses - but with different values! There
is no way this works with other systems or DTS users.

>  
>    reg-names:
>      items:
>        - const: top_cc
> +      - const: reset_cgcr


The 'reg-names' is only a helper, order and contents of 'reg' is fixed.

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
index 9c72b8e..40fc6ab 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
@@ -31,13 +31,18 @@  properties:
   '#clock-cells':
     const: 1
 
+  '#reset-cells':
+    const: 1
+
   reg:
     items:
       - description: LPASS top-cc register
+      - description: LPASS reset-cgcr register
 
   reg-names:
     items:
       - const: top_cc
+      - const: reset_cgcr
 
 required:
   - compatible
@@ -54,10 +59,11 @@  examples:
     #include <dt-bindings/clock/qcom,lpass-sc7280.h>
     clock-controller@3c04000 {
       compatible = "qcom,sc7280-lpasscc";
-      reg = <0x03c04000 0x4>;
-      reg-names = "top_cc";
+      reg = <0x03c04000 0x4>, <0x032a9000 0x1000>;
+      reg-names = "top_cc", "reset_cgcr";
       clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
       clock-names = "iface";
       #clock-cells = <1>;
+      #reset-cells = <1>;
     };
 ...