diff mbox series

[1/3] arm64: dts: qcom: sm8250: Pad addresses to 8 hex digits

Message ID 20221230135044.287874-1-konrad.dybcio@linaro.org
State Accepted
Commit d8b4ee9379e4b6df44bbaf6020461514b401b8f6
Headers show
Series [1/3] arm64: dts: qcom: sm8250: Pad addresses to 8 hex digits | expand

Commit Message

Konrad Dybcio Dec. 30, 2022, 1:50 p.m. UTC
Some addresses were 7-hex-digits long. Fix that.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Krzysztof Kozlowski Dec. 30, 2022, 4:08 p.m. UTC | #1
On 30/12/2022 14:50, Konrad Dybcio wrote:
> - Expand long clock-names into vertical lists
> - Shuffle properties around:
>   - Make sure compatible goes first and status goes last
>   - Make property order consistent between similar nodes
> - Fix up indentation
> - Remove stray newlines
> - Remove a redundant comment about swr2 being associated with TX macro
>   (it's obvious by looking at the label property 10 lines below)
> - Change unnecessary interrupts-extended to interrupts
> - Disable SWR0 and WSA macro by default and enable them on SM8250 MTP and
>   RB5, which were the only users
> - Remove stray #address/size-cells from txmacro, as it's not even
>   supposed to have children

You duplicate here some work:
https://lore.kernel.org/all/20221225115844.55126-4-krzysztof.kozlowski@linaro.org/

and maybe:
https://lore.kernel.org/all/167233461775.1099840.3444272939352778399.b4-ty@kernel.org/

If you wish to avoid trivial cleanup conflicts, feel free to poke to my
pending branch:
https://github.com/krzk/linux/commits/pending/dt-bindings-qcom-new-and-fixes-for-warnings-linux-next

Also, this is a mixture of non-functional changes (re-ordering,
whitespace) with something close to functional (interrupts-extended ->
interrupts, disabling nodes in DTSI). These should be split.



Best regards,
Krzysztof
Konrad Dybcio Dec. 30, 2022, 11:45 p.m. UTC | #2
On 30.12.2022 17:08, Krzysztof Kozlowski wrote:
> On 30/12/2022 14:50, Konrad Dybcio wrote:
>> - Expand long clock-names into vertical lists
>> - Shuffle properties around:
>>   - Make sure compatible goes first and status goes last
>>   - Make property order consistent between similar nodes
>> - Fix up indentation
>> - Remove stray newlines
>> - Remove a redundant comment about swr2 being associated with TX macro
>>   (it's obvious by looking at the label property 10 lines below)
>> - Change unnecessary interrupts-extended to interrupts
>> - Disable SWR0 and WSA macro by default and enable them on SM8250 MTP and
>>   RB5, which were the only users
>> - Remove stray #address/size-cells from txmacro, as it's not even
>>   supposed to have children
> 
> You duplicate here some work:
> https://lore.kernel.org/all/20221225115844.55126-4-krzysztof.kozlowski@linaro.org/
> 
> and maybe:
> https://lore.kernel.org/all/167233461775.1099840.3444272939352778399.b4-ty@kernel.org/
> 
> If you wish to avoid trivial cleanup conflicts, feel free to poke to my
> pending branch:
> https://github.com/krzk/linux/commits/pending/dt-bindings-qcom-new-and-fixes-for-warnings-linux-next
> 
> Also, this is a mixture of non-functional changes (re-ordering,
> whitespace) with something close to functional (interrupts-extended ->
> interrupts, disabling nodes in DTSI). These should be split.
Thanks for pointing this out, I'll resubmit these soon!

Konrad
> 
> 
> 
> Best regards,
> Krzysztof
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index a3aa85a32bf8..3b3ea380c6e6 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2284,7 +2284,7 @@  rxmacro: rxmacro@3200000 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&rx_swr_active>;
 			compatible = "qcom,sm8250-lpass-rx-macro";
-			reg = <0 0x3200000 0 0x1000>;
+			reg = <0 0x03200000 0 0x1000>;
 			status = "disabled";
 
 			clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
@@ -2302,7 +2302,7 @@  rxmacro: rxmacro@3200000 {
 		};
 
 		swr1: soundwire-controller@3210000 {
-			reg = <0 0x3210000 0 0x2000>;
+			reg = <0 0x03210000 0 0x2000>;
 			compatible = "qcom,soundwire-v1.5.1";
 			status = "disabled";
 			interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
@@ -2331,7 +2331,7 @@  txmacro: txmacro@3220000 {
 			pinctrl-names = "default";
 			pinctrl-0 = <&tx_swr_active>;
 			compatible = "qcom,sm8250-lpass-tx-macro";
-			reg = <0 0x3220000 0 0x1000>;
+			reg = <0 0x03220000 0 0x1000>;
 			status = "disabled";
 
 			clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
@@ -2352,7 +2352,7 @@  txmacro: txmacro@3220000 {
 
 		/* tx macro */
 		swr2: soundwire-controller@3230000 {
-			reg = <0 0x3230000 0 0x2000>;
+			reg = <0 0x03230000 0 0x2000>;
 			compatible = "qcom,soundwire-v1.5.1";
 			interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "core";