[edk2] OvmfPkg/PlatformPei: suppress wrong VS2008 warning (use of uninited local)

Message ID 1458344124-12649-1-git-send-email-lersek@redhat.com
State New
Headers show

Commit Message

Laszlo Ersek March 18, 2016, 11:35 p.m.
VS2008 seems to think that the "PciExBarBase" variable (introduced in
commit 7b8fe63561b4) can be evaluated for the
AddReservedMemoryBaseSizeHob() function call with its value being
uninitialized / indeterminate. This is not the case (see
"mHostBridgeDevId"); suppress the warning.

Reported-by: David Woodhouse <dwmw2@infradead.org>
Ref: http://thread.gmane.org/gmane.comp.bios.edk2.devel/8871/focus=9431
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>

---

Notes:
    - Public branch: https://github.com/lersek/edk2/commits/suppress_vs2008
    - Patch formatted with --function-context for easier review

 OvmfPkg/PlatformPei/Platform.c | 1 +
 1 file changed, 1 insertion(+)

-- 
1.8.3.1

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Comments

Laszlo Ersek March 19, 2016, 1:30 a.m. | #1
On 03/19/16 00:35, Laszlo Ersek wrote:
> VS2008 seems to think that the "PciExBarBase" variable (introduced in

> commit 7b8fe63561b4) can be evaluated for the

> AddReservedMemoryBaseSizeHob() function call with its value being

> uninitialized / indeterminate. This is not the case (see

> "mHostBridgeDevId"); suppress the warning.

> 

> Reported-by: David Woodhouse <dwmw2@infradead.org>

> Ref: http://thread.gmane.org/gmane.comp.bios.edk2.devel/8871/focus=9431

> Cc: David Woodhouse <dwmw2@infradead.org>

> Cc: Jordan Justen <jordan.l.justen@intel.com>

> Contributed-under: TianoCore Contribution Agreement 1.0

> Signed-off-by: Laszlo Ersek <lersek@redhat.com>

> ---

> 

> Notes:

>     - Public branch: https://github.com/lersek/edk2/commits/suppress_vs2008

>     - Patch formatted with --function-context for easier review

> 

>  OvmfPkg/PlatformPei/Platform.c | 1 +

>  1 file changed, 1 insertion(+)


Committed / pushed as 02d6f4ce0c84f2d7e9abfcde2e092a5701ff33c4 (now with
the default (UTF-8) commit msg encoding...)

Thanks
Laszlo

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Patch

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 0fc227803a84..509343e0bee5 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -184,99 +184,100 @@  VOID
 MemMapInitialization (
   VOID
   )
 {
   //
   // Create Memory Type Information HOB
   //
   BuildGuidDataHob (
     &gEfiMemoryTypeInformationGuid,
     mDefaultMemoryTypeInformation,
     sizeof(mDefaultMemoryTypeInformation)
     );
 
   //
   // Add PCI IO Port space available for PCI resource allocations.
   //
   BuildResourceDescriptorHob (
     EFI_RESOURCE_IO,
     EFI_RESOURCE_ATTRIBUTE_PRESENT     |
     EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
     PcdGet64 (PcdPciIoBase),
     PcdGet64 (PcdPciIoSize)
     );
 
   //
   // Video memory + Legacy BIOS region
   //
   AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
 
   if (!mXen) {
     UINT32  TopOfLowRam;
     UINT64  PciExBarBase;
     UINT32  PciBase;
     UINT32  PciSize;
 
     TopOfLowRam = GetSystemMemorySizeBelow4gb ();
+    PciExBarBase = 0;
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
       //
       // The MMCONFIG area is expected to fall between the top of low RAM and
       // the base of the 32-bit PCI host aperture.
       //
       PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
       ASSERT (TopOfLowRam <= PciExBarBase);
       ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
       PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
     } else {
       PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
     }
 
     //
     // address       purpose   size
     // ------------  --------  -------------------------
     // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)
     // 0xFC000000    gap                           44 MB
     // 0xFEC00000    IO-APIC                        4 KB
     // 0xFEC01000    gap                         1020 KB
     // 0xFED00000    HPET                           1 KB
     // 0xFED00400    gap                          111 KB
     // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
     // 0xFED20000    gap                          896 KB
     // 0xFEE00000    LAPIC                          1 MB
     //
     PciSize = 0xFC000000 - PciBase;
     AddIoMemoryBaseSizeHob (PciBase, PciSize);
     PcdSet64 (PcdPciMmio32Base, PciBase);
     PcdSet64 (PcdPciMmio32Size, PciSize);
     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
     if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
       AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
       //
       // Note: there should be an
       //
       //   AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);
       //
       // call below, just like the one above for RCBA. However, Linux insists
       // that the MMCONFIG area be marked in the E820 or UEFI memory map as
       // "reserved memory" -- Linux does not content itself with a simple gap
       // in the memory map wherever the MCFG ACPI table points to.
       //
       // This appears to be a safety measure. The PCI Firmware Specification
       // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can
       // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory
       // [...]". (Emphasis added here.)
       //
       // Normally we add memory resource descriptor HOBs in
       // QemuInitializeRam(), and pre-allocate from those with memory
       // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area
       // is most definitely not RAM; so, as an exception, cover it with
       // uncacheable reserved memory right here.
       //
       AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);
       BuildMemoryAllocationHob (PciExBarBase, SIZE_256MB,
         EfiReservedMemoryType);
     }
     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
   }
 }