| Message ID | 20230115124143.464809-2-dmitry.baryshkov@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/2] drm/msm/dpu: fix clocks settings for msm8998 SSPP blocks | expand |
On 15/01/2023 13:41, Dmitry Baryshkov wrote: > DPU driver has been using the DPU_CLK_CTRL_CURSOR prefix for the DMA > SSPP blocks used for the cursor planes. This has lead to the confusion > at least for the MSM8998 platform. In preparation to supporting the > cursor SSPP blocks, use proper enum values to index DMA SSPP clock > controls. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 64 +++++++++---------- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 + > 2 files changed, 34 insertions(+), 32 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index ad0c55464154..b0f6e071fe4b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -522,9 +522,9 @@ static const struct dpu_mdp_cfg sdm845_mdp[] = { > .reg_off = 0x2AC, .bit_off = 8}, > .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > .reg_off = 0x2B4, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { > .reg_off = 0x2BC, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { > .reg_off = 0x2C4, .bit_off = 8}, > }, > }; > @@ -539,9 +539,9 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = { > .reg_off = 0x2AC, .bit_off = 0}, > .clk_ctrls[DPU_CLK_CTRL_DMA0] = { > .reg_off = 0x2AC, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > .reg_off = 0x2B4, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { > .reg_off = 0x2C4, .bit_off = 8}, > }, > }; > @@ -564,9 +564,9 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = { > .reg_off = 0x2AC, .bit_off = 8}, > .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > .reg_off = 0x2B4, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { > .reg_off = 0x2BC, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { > .reg_off = 0x2C4, .bit_off = 8}, > }, > }; > @@ -602,9 +602,9 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { > .reg_off = 0x2AC, .bit_off = 8}, > .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > .reg_off = 0x2B4, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { > .reg_off = 0x2BC, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { > .reg_off = 0x2C4, .bit_off = 8}, > .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { > .reg_off = 0x2BC, .bit_off = 20}, > @@ -631,9 +631,9 @@ static const struct dpu_mdp_cfg sm8350_mdp[] = { > .reg_off = 0x2ac, .bit_off = 8}, > .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > .reg_off = 0x2b4, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { > .reg_off = 0x2bc, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { > .reg_off = 0x2c4, .bit_off = 8}, > .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { > .reg_off = 0x2bc, .bit_off = 20}, > @@ -658,9 +658,9 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = { > .reg_off = 0x2AC, .bit_off = 8}, > .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > .reg_off = 0x2B4, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { > .reg_off = 0x2BC, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { > .reg_off = 0x2C4, .bit_off = 8}, > .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { > .reg_off = 0x2BC, .bit_off = 20}, > @@ -676,9 +676,9 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = { > .reg_off = 0x2AC, .bit_off = 0}, > .clk_ctrls[DPU_CLK_CTRL_DMA0] = { > .reg_off = 0x2AC, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > .reg_off = 0x2B4, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { > .reg_off = 0x2C4, .bit_off = 8}, > }, > }; > @@ -696,8 +696,8 @@ static const struct dpu_mdp_cfg sc8280xp_mdp[] = { > .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0}, > .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8}, > .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x2bc, .bit_off = 8}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x2c4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8}, > .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20}, > }, > }; > @@ -724,9 +724,9 @@ static const struct dpu_mdp_cfg sm8550_mdp[] = { > .reg_off = 0x28330, .bit_off = 0}, > .clk_ctrls[DPU_CLK_CTRL_DMA3] = { > .reg_off = 0x2a330, .bit_off = 0}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA4] = { > .reg_off = 0x2c330, .bit_off = 0}, > - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .clk_ctrls[DPU_CLK_CTRL_DMA5] = { > .reg_off = 0x2e330, .bit_off = 0}, > .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { > .reg_off = 0x2bc, .bit_off = 20}, > @@ -1199,9 +1199,9 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = { > SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, > sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), > SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), > }; > > static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = > @@ -1216,9 +1216,9 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = { > SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, > sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), > SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), > }; > > static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = > @@ -1254,9 +1254,9 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { > SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, > sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), > SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), > }; > > static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 = > @@ -1282,9 +1282,9 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { > SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, > sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), > SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), > }; > > static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 = > @@ -1316,9 +1316,9 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { > SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_SDM845_MASK, > sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), > SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, DMA_CURSOR_SDM845_MASK, > - sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4), > SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, DMA_CURSOR_SDM845_MASK, > - sd8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > + sd8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5), > }; > > static const struct dpu_sspp_cfg sc7280_sspp[] = { > @@ -1327,9 +1327,9 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = { > SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, > sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), > SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), > }; > > static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_0 = > @@ -1355,9 +1355,9 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = { > SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, > sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), > SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), > }; > > #define _VIG_SBLK_NOSCALE(num, sdma_pri) \ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 56d98b4dd2ac..9c96920e1849 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -513,6 +513,8 @@ enum dpu_clk_ctrl_type { > DPU_CLK_CTRL_DMA1, > DPU_CLK_CTRL_DMA2, > DPU_CLK_CTRL_DMA3, > + DPU_CLK_CTRL_DMA4, > + DPU_CLK_CTRL_DMA5, > DPU_CLK_CTRL_CURSOR0, > DPU_CLK_CTRL_CURSOR1, > DPU_CLK_CTRL_INLINE_ROT0_SSPP, Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550 on top of next-20230116
On 2023-01-15 14:41:43, Dmitry Baryshkov wrote: > DPU driver has been using the DPU_CLK_CTRL_CURSOR prefix for the DMA > SSPP blocks used for the cursor planes. This has lead to the confusion > at least for the MSM8998 platform. In preparation to supporting the > cursor SSPP blocks, use proper enum values to index DMA SSPP clock > controls. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> > Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550 on top of next-20230116 Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> One question follows... > --- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 64 +++++++++---------- > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 + > 2 files changed, 34 insertions(+), 32 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index ad0c55464154..b0f6e071fe4b 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c <snip> > @@ -1199,9 +1199,9 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = { > SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, > sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, Are these DMA pipes with CURSOR support, or how should I see this? For MSM8998 I suggested to remove the _CURSOR bit since it has two dedicated cursor pipes (not yet represented in the catalog) but these SoCs don't seem to have those. - Marijn > - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), > SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), > }; > > static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = > @@ -1216,9 +1216,9 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = { > SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, > sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), > SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), > }; > > static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = > @@ -1254,9 +1254,9 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { > SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, > sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), > SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), > }; > > static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 = > @@ -1282,9 +1282,9 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { > SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, > sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), > SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), > }; > > static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 = > @@ -1316,9 +1316,9 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { > SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_SDM845_MASK, > sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), > SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, DMA_CURSOR_SDM845_MASK, > - sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4), > SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, DMA_CURSOR_SDM845_MASK, > - sd8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > + sd8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5), > }; > > static const struct dpu_sspp_cfg sc7280_sspp[] = { > @@ -1327,9 +1327,9 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = { > SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, > sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), > SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), > }; > > static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_0 = > @@ -1355,9 +1355,9 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = { > SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, > sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), > SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, > - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), > }; > > #define _VIG_SBLK_NOSCALE(num, sdma_pri) \ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 56d98b4dd2ac..9c96920e1849 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -513,6 +513,8 @@ enum dpu_clk_ctrl_type { > DPU_CLK_CTRL_DMA1, > DPU_CLK_CTRL_DMA2, > DPU_CLK_CTRL_DMA3, > + DPU_CLK_CTRL_DMA4, > + DPU_CLK_CTRL_DMA5, > DPU_CLK_CTRL_CURSOR0, > DPU_CLK_CTRL_CURSOR1, > DPU_CLK_CTRL_INLINE_ROT0_SSPP,
On 24/01/2023 12:13, Marijn Suijten wrote: > On 2023-01-15 14:41:43, Dmitry Baryshkov wrote: >> DPU driver has been using the DPU_CLK_CTRL_CURSOR prefix for the DMA >> SSPP blocks used for the cursor planes. This has lead to the confusion >> at least for the MSM8998 platform. In preparation to supporting the >> cursor SSPP blocks, use proper enum values to index DMA SSPP clock >> controls. >> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> >> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> >> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550 on top of next-20230116 > > Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> > > One question follows... > >> --- >> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 64 +++++++++---------- >> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 + >> 2 files changed, 34 insertions(+), 32 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> index ad0c55464154..b0f6e071fe4b 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > <snip> >> @@ -1199,9 +1199,9 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = { >> SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, >> sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), >> SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > > Are these DMA pipes with CURSOR support, or how should I see this? For > MSM8998 I suggested to remove the _CURSOR bit since it has two dedicated > cursor pipes (not yet represented in the catalog) but these SoCs don't > seem to have those. > As I wrote earlier, this part just marks them to be used for HW cursor support.
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index ad0c55464154..b0f6e071fe4b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -522,9 +522,9 @@ static const struct dpu_mdp_cfg sdm845_mdp[] = { .reg_off = 0x2AC, .bit_off = 8}, .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2B4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2BC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2C4, .bit_off = 8}, }, }; @@ -539,9 +539,9 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = { .reg_off = 0x2AC, .bit_off = 0}, .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2AC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2B4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2C4, .bit_off = 8}, }, }; @@ -564,9 +564,9 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = { .reg_off = 0x2AC, .bit_off = 8}, .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2B4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2BC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2C4, .bit_off = 8}, }, }; @@ -602,9 +602,9 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { .reg_off = 0x2AC, .bit_off = 8}, .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2B4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2BC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2C4, .bit_off = 8}, .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2BC, .bit_off = 20}, @@ -631,9 +631,9 @@ static const struct dpu_mdp_cfg sm8350_mdp[] = { .reg_off = 0x2ac, .bit_off = 8}, .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8}, .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20}, @@ -658,9 +658,9 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = { .reg_off = 0x2AC, .bit_off = 8}, .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2B4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2BC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2C4, .bit_off = 8}, .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2BC, .bit_off = 20}, @@ -676,9 +676,9 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = { .reg_off = 0x2AC, .bit_off = 0}, .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2AC, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2B4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2C4, .bit_off = 8}, }, }; @@ -696,8 +696,8 @@ static const struct dpu_mdp_cfg sc8280xp_mdp[] = { .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0}, .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8}, .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x2bc, .bit_off = 8}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x2c4, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8}, + .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8}, .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20}, }, }; @@ -724,9 +724,9 @@ static const struct dpu_mdp_cfg sm8550_mdp[] = { .reg_off = 0x28330, .bit_off = 0}, .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { + .clk_ctrls[DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0}, - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { + .clk_ctrls[DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0}, .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20}, @@ -1199,9 +1199,9 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = { SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), }; static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = @@ -1216,9 +1216,9 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = { SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), }; static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = @@ -1254,9 +1254,9 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), }; static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 = @@ -1282,9 +1282,9 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), }; static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 = @@ -1316,9 +1316,9 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_SDM845_MASK, sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, DMA_CURSOR_SDM845_MASK, - sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4), SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, DMA_CURSOR_SDM845_MASK, - sd8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), + sd8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5), }; static const struct dpu_sspp_cfg sc7280_sspp[] = { @@ -1327,9 +1327,9 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = { SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), }; static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_0 = @@ -1355,9 +1355,9 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = { SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), }; #define _VIG_SBLK_NOSCALE(num, sdma_pri) \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 56d98b4dd2ac..9c96920e1849 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -513,6 +513,8 @@ enum dpu_clk_ctrl_type { DPU_CLK_CTRL_DMA1, DPU_CLK_CTRL_DMA2, DPU_CLK_CTRL_DMA3, + DPU_CLK_CTRL_DMA4, + DPU_CLK_CTRL_DMA5, DPU_CLK_CTRL_CURSOR0, DPU_CLK_CTRL_CURSOR1, DPU_CLK_CTRL_INLINE_ROT0_SSPP,
DPU driver has been using the DPU_CLK_CTRL_CURSOR prefix for the DMA SSPP blocks used for the cursor planes. This has lead to the confusion at least for the MSM8998 platform. In preparation to supporting the cursor SSPP blocks, use proper enum values to index DMA SSPP clock controls. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 64 +++++++++---------- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 + 2 files changed, 34 insertions(+), 32 deletions(-)