| Message ID | 20230114233455.2005047-3-martin.blumenstingl@googlemail.com |
|---|---|
| State | Accepted |
| Commit | 46f73c1c037eed8e5fd61cc39c77b0988148b50b |
| Headers | show |
| Series | ARM: dts: meson: Add more L2 (PL310) cache properties | expand |
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index cf9c04a61ba3..2d80c009bdfa 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -643,6 +643,9 @@ &L2 { arm,filter-ranges = <0x100000 0xc0000000>; prefetch-data = <1>; prefetch-instr = <1>; + arm,prefetch-offset = <7>; + arm,double-linefill = <1>; + arm,prefetch-drop = <1>; arm,shared-override; };
Add more L2 cache properties which are used by the 3.10 vendor kernel but have not made it upstream yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- arch/arm/boot/dts/meson8b.dtsi | 3 +++ 1 file changed, 3 insertions(+)