| Message ID | 20230124180127.1881110-21-alex.bennee@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | maintainer tree pre-PR (testing/docs/semihosting/plugins) | expand |
On 24/01/2023 19.01, Alex Bennée wrote: > This affects both system and user mode emulation so we should probably > list it up front. > > Acked-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> > > --- > v2 > - HPs -> HP's > - MIPs-like -> MIPS-like > --- > docs/about/emulation.rst | 103 ++++++++++++++++++++++++++++++++++ > docs/about/index.rst | 1 + > docs/devel/tcg-plugins.rst | 2 + > docs/system/arm/emulation.rst | 2 + > 4 files changed, 108 insertions(+) > create mode 100644 docs/about/emulation.rst > > diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst > new file mode 100644 > index 0000000000..bdc0630b35 > --- /dev/null > +++ b/docs/about/emulation.rst > @@ -0,0 +1,103 @@ > +Emulation > +========= > + > +QEMU's Tiny Code Generator (TCG) gives it the ability to emulate a I'd maybe rather say "provides" instead of "gives it". > +number of CPU architectures on any supported platform. Both I'd maybe add a "host" between "supported" and "platform. > +:ref:`System Emulation` and :ref:`User Mode Emulation` are supported > +depending on the guest architecture. > + > +.. list-table:: Supported Guest Architectures for Emulation > + :widths: 30 10 10 50 > + :header-rows: 1 > + > + * - Architecture (qemu name) > + - System > + - User-mode Maybe just use "User" instead of "User-mode" to make the column smaller? > + - Notes > + * - Alpha > + - Yes > + - Yes > + - Legacy 64 bit RISC ISA developed by DEC > + * - Arm (arm, aarch64) > + - Yes > + - Yes > + - Wide range of features, see :ref:`Arm Emulation` for details > + * - AVR > + - Yes > + - No > + - 8 bit micro controller, often used in maker projects > + * - Cris > + - Yes > + - Yes > + - Embedded RISC chip developed by AXIS > + * - Hexagon > + - No > + - Yes > + - Family of DSPs by Qualcomm > + * - PA-RISC (hppa) > + - Yes > + - Yes > + - A legacy RISC system used in HP's old minicomputers > + * - x86 (i386, x86_64) > + - Yes > + - Yes > + - The ubiquitous desktop PC CPU architecture, 32 and 64 bit. > + * - Loongarch > + - Yes > + - Yes > + - A MIPS-like 64bit RISC architecture developed in China > + * - m68k > + - Yes Would it be possible to link the "Yes" entries in the "System" column to corresponding target-*.rst files? E.g. docs/system/target-m68k.rst for the m68k entry? > + - Yes > + - Motorola 68000 variants and ColdFire > + * - Microblaze > + - Yes > + - Yes > + - RISC based soft-core by Xilinx > + * - MIPS (mips, mipsel, mips64, mips64el) The table renders very badly for me, the last column is cut off and you need to scroll to see its contents. This seems mainly to happen since this MIPS entry is very long. Could the information in the parentheses maybe be shortened to "(mips*)" or be dropped completely? Thomas
On 25/1/23 08:58, Thomas Huth wrote: > On 24/01/2023 19.01, Alex Bennée wrote: >> This affects both system and user mode emulation so we should probably >> list it up front. >> >> Acked-by: Richard Henderson <richard.henderson@linaro.org> >> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> >> >> --- >> v2 >> - HPs -> HP's >> - MIPs-like -> MIPS-like >> --- >> docs/about/emulation.rst | 103 ++++++++++++++++++++++++++++++++++ >> docs/about/index.rst | 1 + >> docs/devel/tcg-plugins.rst | 2 + >> docs/system/arm/emulation.rst | 2 + >> 4 files changed, 108 insertions(+) >> create mode 100644 docs/about/emulation.rst >> >> diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst >> new file mode 100644 >> index 0000000000..bdc0630b35 >> --- /dev/null >> +++ b/docs/about/emulation.rst >> @@ -0,0 +1,103 @@ >> +Emulation >> +========= >> + >> +QEMU's Tiny Code Generator (TCG) gives it the ability to emulate a > > I'd maybe rather say "provides" instead of "gives it". > >> +number of CPU architectures on any supported platform. Both > > I'd maybe add a "host" between "supported" and "platform. > >> +:ref:`System Emulation` and :ref:`User Mode Emulation` are supported >> +depending on the guest architecture. >> + >> +.. list-table:: Supported Guest Architectures for Emulation >> + :widths: 30 10 10 50 >> + :header-rows: 1 >> + >> + * - Architecture (qemu name) >> + - System >> + - User-mode > > Maybe just use "User" instead of "User-mode" to make the column smaller? > >> + - Notes >> + * - Alpha >> + - Yes >> + - Yes >> + - Legacy 64 bit RISC ISA developed by DEC >> + * - Arm (arm, aarch64) >> + - Yes >> + - Yes >> + - Wide range of features, see :ref:`Arm Emulation` for details >> + * - AVR >> + - Yes >> + - No >> + - 8 bit micro controller, often used in maker projects >> + * - Cris >> + - Yes >> + - Yes >> + - Embedded RISC chip developed by AXIS >> + * - Hexagon >> + - No >> + - Yes >> + - Family of DSPs by Qualcomm >> + * - PA-RISC (hppa) >> + - Yes >> + - Yes >> + - A legacy RISC system used in HP's old minicomputers >> + * - x86 (i386, x86_64) >> + - Yes >> + - Yes >> + - The ubiquitous desktop PC CPU architecture, 32 and 64 bit. >> + * - Loongarch >> + - Yes >> + - Yes >> + - A MIPS-like 64bit RISC architecture developed in China >> + * - m68k >> + - Yes > > Would it be possible to link the "Yes" entries in the "System" column to > corresponding target-*.rst files? E.g. docs/system/target-m68k.rst for > the m68k entry? > >> + - Yes >> + - Motorola 68000 variants and ColdFire >> + * - Microblaze >> + - Yes >> + - Yes >> + - RISC based soft-core by Xilinx >> + * - MIPS (mips, mipsel, mips64, mips64el) > > The table renders very badly for me, the last column is cut off and you > need to scroll to see its contents. This seems mainly to happen since > this MIPS entry is very long. Could the information in the parentheses > maybe be shortened to "(mips*)" or be dropped completely? Or "32 and 64 bit".
diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst new file mode 100644 index 0000000000..bdc0630b35 --- /dev/null +++ b/docs/about/emulation.rst @@ -0,0 +1,103 @@ +Emulation +========= + +QEMU's Tiny Code Generator (TCG) gives it the ability to emulate a +number of CPU architectures on any supported platform. Both +:ref:`System Emulation` and :ref:`User Mode Emulation` are supported +depending on the guest architecture. + +.. list-table:: Supported Guest Architectures for Emulation + :widths: 30 10 10 50 + :header-rows: 1 + + * - Architecture (qemu name) + - System + - User-mode + - Notes + * - Alpha + - Yes + - Yes + - Legacy 64 bit RISC ISA developed by DEC + * - Arm (arm, aarch64) + - Yes + - Yes + - Wide range of features, see :ref:`Arm Emulation` for details + * - AVR + - Yes + - No + - 8 bit micro controller, often used in maker projects + * - Cris + - Yes + - Yes + - Embedded RISC chip developed by AXIS + * - Hexagon + - No + - Yes + - Family of DSPs by Qualcomm + * - PA-RISC (hppa) + - Yes + - Yes + - A legacy RISC system used in HP's old minicomputers + * - x86 (i386, x86_64) + - Yes + - Yes + - The ubiquitous desktop PC CPU architecture, 32 and 64 bit. + * - Loongarch + - Yes + - Yes + - A MIPS-like 64bit RISC architecture developed in China + * - m68k + - Yes + - Yes + - Motorola 68000 variants and ColdFire + * - Microblaze + - Yes + - Yes + - RISC based soft-core by Xilinx + * - MIPS (mips, mipsel, mips64, mips64el) + - Yes + - Yes + - Venerable RISC architecture originally out of Stanford University + * - Nios2 + - Yes + - Yes + - 32 bit embedded soft-core by Altera + * - OpenRISC + - Yes + - Yes + - Open source RISC architecture developed by the OpenRISC community + * - Power (ppc, ppc64) + - Yes + - Yes + - A general purpose RISC architecture now managed by IBM + * - RISC-V + - Yes + - Yes + - An open standard RISC ISA maintained by RISC-V International + * - RX + - Yes + - No + - A 32 bit micro controller developed by Renesas + * - s390x + - Yes + - Yes + - A 64 bit CPU found in IBM's System Z mainframes + * - sh4 + - Yes + - Yes + - A 32 bit RISC embedded CPU developed by Hitachi + * - SPARC (sparc, sparc64) + - Yes + - Yes + - A RISC ISA originally developed by Sun Microsystems + * - Tricore + - Yes + - No + - A 32 bit RISC/uController/DSP developed by Infineon + * - Xtensa + - Yes + - Yes + - A configurable 32 bit soft core now owned by Cadence + +A number of features are are only available when running under +emulation including :ref:`Record/Replay<replay>` and :ref:`TCG Plugins`. diff --git a/docs/about/index.rst b/docs/about/index.rst index bae1309cc6..b00b584b31 100644 --- a/docs/about/index.rst +++ b/docs/about/index.rst @@ -23,6 +23,7 @@ allows you to create, convert and modify disk images. :maxdepth: 2 build-platforms + emulation deprecated removed-features license diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst index 9740a70406..81dcd43a61 100644 --- a/docs/devel/tcg-plugins.rst +++ b/docs/devel/tcg-plugins.rst @@ -3,6 +3,8 @@ Copyright (c) 2019, Linaro Limited Written by Emilio Cota and Alex Bennée +.. _TCG Plugins: + QEMU TCG Plugins ================ diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index b33d7c28dc..b87e064d9d 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -1,3 +1,5 @@ +.. _Arm Emulation: + A-profile CPU architecture support ==================================