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[v2] dt-bindings: iommu: renesas,ipmmu-vmsa: Update for R-Car Gen4

Message ID 20230127140446.1728102-1-yoshihiro.shimoda.uh@renesas.com
State New
Headers show
Series [v2] dt-bindings: iommu: renesas,ipmmu-vmsa: Update for R-Car Gen4 | expand

Commit Message

Yoshihiro Shimoda Jan. 27, 2023, 2:04 p.m. UTC 
Since R-Car Gen4 doens't have the main IPMMU IMSSTR register, update
the renesas,ipmmu-main property which allows to only set the first
argument for R-Car Gen4.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
Changes from v1:
https://lore.kernel.org/all/20230123012940.1250879-1-yoshihiro.shimoda.uh@renesas.com/
 - Change number of argument for R-Car Gen4 instead of "module id".
   On the discussion, using 'minItems' is a solution. But, it causes
   "too short" errors on dtbs_check. So, using "oneOf" instead.

 .../bindings/iommu/renesas,ipmmu-vmsa.yaml         | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)
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Patch

diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
index 72308a4c14e7..8e8f79f612e5 100644
--- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
+++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
@@ -73,12 +73,16 @@  properties:
 
   renesas,ipmmu-main:
     $ref: /schemas/types.yaml#/definitions/phandle-array
-    items:
+    oneOf:
+      - items:
+          - items:
+              - description: phandle to main IPMMU
+              - description: the interrupt bit number associated with the particular
+                  cache IPMMU device. The interrupt bit number needs to match the main
+                  IPMMU IMSSTR register. Only used by cache IPMMU instances.
       - items:
-          - description: phandle to main IPMMU
-          - description: the interrupt bit number associated with the particular
-              cache IPMMU device. The interrupt bit number needs to match the main
-              IPMMU IMSSTR register. Only used by cache IPMMU instances.
+          - items:
+              - description: phandle to main IPMMU
     description:
       Reference to the main IPMMU phandle plus 1 cell. The cell is
       the interrupt bit number associated with the particular cache IPMMU