| Message ID | 20230130153252.2310882-3-konrad.dybcio@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | SM6(11|12|37)5 GPUCC | expand |
diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index d8fc7b93ef6d..773f760a4590 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -41,6 +41,8 @@ struct clk_branch { #define CBCR_FORCE_MEM_CORE_ON BIT(14) #define CBCR_FORCE_MEM_PERIPH_ON BIT(13) #define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) +#define CBCR_WAKEUP GENMASK(11, 8) +#define CBCR_SLEEP GENMASK(7, 4) static inline void qcom_branch_set_force_mem_core(struct regmap *regmap, u32 reg, bool on) {
HLOS-controlled branch clocks on non-ancient Qualcomm platforms feature SLEEP and WAKE fields which can be written to to configure how long the clock hardware should wait internally before being (un)gated. Some very sensitive clocks need to have these values programmed to prevent putting the hardware in a not-exactly-good state. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- v2 -> v3: - New patch drivers/clk/qcom/clk-branch.h | 2 ++ 1 file changed, 2 insertions(+)