diff mbox series

[RESEND,v8,4/5] clk: qcom: lpassaudiocc-sc7280: Merge AHB clocks into lpass_aon

Message ID 20230215151330.539885-5-quic_mohs@quicinc.com
State New
Headers show
Series Add resets for ADSP based audio clock controller driver | expand

Commit Message

Mohammad Rafi Shaik Feb. 15, 2023, 3:13 p.m. UTC 
From: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>

Merge AHBM and AHBS clocks into lpass_aon clk_regmap structure as they
are using same register space.
Modify AHB clocks explicit registration, from qcom_cc_probe to
com_cc_probe_by_index.
In existing implementation, Q6 AHB clocks and lpass_aon clocks are
being registered exclusively and overlapping if both of them are
to be used. The regmap region used by Q6 AHB clocks is <0x03389000 0x24>
and of lpass_aon clocks is <0x03380000 0x30000>.
This is required to avoid such overlapping and to register
Q6 AHB clocks and lpass_aon clocks simultaneously.

Fixes: 4ab43d171181 ("clk: qcom: Add lpass clock controller driver for SC7280")
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
---
 drivers/clk/qcom/lpassaudiocc-sc7280.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

Comments

Stephen Boyd Feb. 23, 2023, 6:59 p.m. UTC | #1 
Quoting Mohammad Rafi Shaik (2023-02-23 02:19:30)
>
> On 2/16/2023 11:01 AM, Stephen Boyd wrote:
> > Quoting Mohammad Rafi Shaik (2023-02-15 07:13:29)
> >> @@ -828,8 +830,9 @@ static int lpass_aon_cc_sc7280_probe(struct platform_device *pdev)
> >>          if (of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
> >>                  lpass_audio_cc_sc7280_regmap_config.name = "cc";
> >>                  desc = &lpass_cc_sc7280_desc;
> >> -               ret = qcom_cc_probe(pdev, desc);
> >> -               goto exit;
> >> +               ret = qcom_cc_probe_by_index(pdev, 1, desc);
> > Where is the patch to the binding yaml file?
> Thanks for comment.
>
> The dtbinding  yaml file for this is already present in existing yaml.
>
> Below is the snippet for the same:
>
> compatible = "qcom,sc7280-lpassaoncc";
> reg = <0x3380000 0x30000>;
>
> Actually what ever the  CC register region <required range is  0x3389000
> 0x24> which we are accessing is already present in the above reg map
> range of dtsi, so we have not updated the
> /devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml file.
>

The usage of '1' in qcom_cc_probe_by_index() means that the reg property
should have at least two addresses. The example you pasted above shows
only one reg address. The binding needs an update for two registers,
where is that?
diff mbox series

Patch

diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
index 1339f9211a14..533d68d80538 100644
--- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
+++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
@@ -660,6 +660,8 @@  static struct clk_regmap *lpass_aon_cc_sc7280_clocks[] = {
 	[LPASS_AON_CC_TX_MCLK_2X_CLK] = &lpass_aon_cc_tx_mclk_2x_clk.clkr,
 	[LPASS_AON_CC_TX_MCLK_CLK] = &lpass_aon_cc_tx_mclk_clk.clkr,
 	[LPASS_AON_CC_TX_MCLK_RCG_CLK_SRC] = &lpass_aon_cc_tx_mclk_rcg_clk_src.clkr,
+	[LPASS_Q6_AHBM_CLK] = &lpass_q6ss_ahbm_clk.clkr,
+	[LPASS_Q6_AHBS_CLK] = &lpass_q6ss_ahbs_clk.clkr,
 };
 
 static struct gdsc *lpass_aon_cc_sc7280_gdscs[] = {
@@ -828,8 +830,9 @@  static int lpass_aon_cc_sc7280_probe(struct platform_device *pdev)
 	if (of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) {
 		lpass_audio_cc_sc7280_regmap_config.name = "cc";
 		desc = &lpass_cc_sc7280_desc;
-		ret = qcom_cc_probe(pdev, desc);
-		goto exit;
+		ret = qcom_cc_probe_by_index(pdev, 1, desc);
+		if (!ret)
+			goto exit;
 	}
 
 	lpass_audio_cc_sc7280_regmap_config.name = "lpasscc_aon";