@@ -461,6 +461,10 @@ lt9611_out: endpoint {
};
};
+&ice {
+ status = "okay";
+};
+
&mdss {
status = "okay";
};
@@ -3989,9 +3989,8 @@ system-cache-controller@19200000 {
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
- reg = <0 0x01d84000 0 0x3000>,
- <0 0x01d88000 0 0x8000>;
- reg-names = "std", "ice";
+ reg = <0 0x01d84000 0 0x3000>;
+ reg-names = "std";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
@@ -4015,8 +4014,7 @@ ufs_mem_hc: ufshc@1d84000 {
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
- "rx_lane1_sync_clk",
- "ice_core_clk";
+ "rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
@@ -4025,8 +4023,7 @@ ufs_mem_hc: ufshc@1d84000 {
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
- <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<75000000 300000000>,
<0 0>,
@@ -4035,8 +4032,17 @@ ufs_mem_hc: ufshc@1d84000 {
<75000000 300000000>,
<0 0>,
<0 0>,
- <0 0>,
- <75000000 300000000>;
+ <0 0>;
+ qcom,ice = <&ice>;
+
+ status = "disabled";
+ };
+
+ ice: inline-crypto-engine {
+ compatible = "qcom,inline-crypto-engine";
+ reg = <0 0x01d88000 0 0x8000>;
+ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+
status = "disabled";
};
Drop all values related to the ICE from the UFS HC node and add a dedicated ICE node. Also enable it in HDK board dts. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 ++++ arch/arm64/boot/dts/qcom/sm8450.dtsi | 24 +++++++++++++++--------- 2 files changed, 19 insertions(+), 9 deletions(-)