diff mbox series

[v3,1/4] util/cacheflush: fix cache on windows-arm64

Message ID 20230220111215.27471-2-pierrick.bouvier@linaro.org
State Superseded
Headers show
Series Adds support for running QEMU natively on windows-arm64 | expand

Commit Message

Pierrick Bouvier Feb. 20, 2023, 11:12 a.m. UTC
ctr_el0 access is privileged on this platform and fails as an illegal
instruction.

Windows does not offer a way to flush data cache from userspace, and
only FlushInstructionCache is available in Windows API.

The generic implementation of flush_idcache_range uses,
__builtin___clear_cache, which already use the FlushInstructionCache
function. So we rely on that.

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 util/cacheflush.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

Comments

Pierrick Bouvier Feb. 20, 2023, 3:16 p.m. UTC | #1
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

On 2/20/23 12:12, Pierrick Bouvier wrote:
> ctr_el0 access is privileged on this platform and fails as an illegal
> instruction.
> 
> Windows does not offer a way to flush data cache from userspace, and
> only FlushInstructionCache is available in Windows API.
> 
> The generic implementation of flush_idcache_range uses,
> __builtin___clear_cache, which already use the FlushInstructionCache
> function. So we rely on that.
> 
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> ---
>   util/cacheflush.c | 14 +++++++++++---
>   1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/util/cacheflush.c b/util/cacheflush.c
> index 2c2c73e085..06c2333a60 100644
> --- a/util/cacheflush.c
> +++ b/util/cacheflush.c
> @@ -121,8 +121,12 @@ static void sys_cache_info(int *isize, int *dsize)
>   static bool have_coherent_icache;
>   #endif
>   
> -#if defined(__aarch64__) && !defined(CONFIG_DARWIN)
> -/* Apple does not expose CTR_EL0, so we must use system interfaces. */
> +#if defined(__aarch64__) && !defined(CONFIG_DARWIN) && !defined(CONFIG_WIN32)
> +/*
> + * Apple does not expose CTR_EL0, so we must use system interfaces.
> + * Windows neither, but we use a generic implementation of flush_idcache_range
> + * in this case.
> + */
>   static uint64_t save_ctr_el0;
>   static void arch_cache_info(int *isize, int *dsize)
>   {
> @@ -225,7 +229,11 @@ static void __attribute__((constructor)) init_cache_info(void)
>   
>   /* Caches are coherent and do not require flushing; symbol inline. */
>   
> -#elif defined(__aarch64__)
> +#elif defined(__aarch64__) && !defined(CONFIG_WIN32)
> +/*
> + * For Windows, we use generic implementation of flush_idcache_range, that
> + * performs a call to FlushInstructionCache, through __builtin___clear_cache.
> + */
>   
>   #ifdef CONFIG_DARWIN
>   /* Apple does not expose CTR_EL0, so we must use system interfaces. */
diff mbox series

Patch

diff --git a/util/cacheflush.c b/util/cacheflush.c
index 2c2c73e085..06c2333a60 100644
--- a/util/cacheflush.c
+++ b/util/cacheflush.c
@@ -121,8 +121,12 @@  static void sys_cache_info(int *isize, int *dsize)
 static bool have_coherent_icache;
 #endif
 
-#if defined(__aarch64__) && !defined(CONFIG_DARWIN)
-/* Apple does not expose CTR_EL0, so we must use system interfaces. */
+#if defined(__aarch64__) && !defined(CONFIG_DARWIN) && !defined(CONFIG_WIN32)
+/*
+ * Apple does not expose CTR_EL0, so we must use system interfaces.
+ * Windows neither, but we use a generic implementation of flush_idcache_range
+ * in this case.
+ */
 static uint64_t save_ctr_el0;
 static void arch_cache_info(int *isize, int *dsize)
 {
@@ -225,7 +229,11 @@  static void __attribute__((constructor)) init_cache_info(void)
 
 /* Caches are coherent and do not require flushing; symbol inline. */
 
-#elif defined(__aarch64__)
+#elif defined(__aarch64__) && !defined(CONFIG_WIN32)
+/*
+ * For Windows, we use generic implementation of flush_idcache_range, that
+ * performs a call to FlushInstructionCache, through __builtin___clear_cache.
+ */
 
 #ifdef CONFIG_DARWIN
 /* Apple does not expose CTR_EL0, so we must use system interfaces. */