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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/starfive,jh7110-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive Watchdog
+
+maintainers:
+ - Samin Guo <samin.guo@starfivetech.com>
+ - Xingyu Wu <xingyu.wu@starfivetech.com>
+
+description:
+ The watchdog is a 32 bit counter and has two timeout phases.
+ At the first phase, the signal of watchdog interrupt output(WDOGINT)
+ will rise when counter is 0. The counter will reload the timeout value.
+ And then, if counter decreases to 0 again and WDOGINT isn't cleared,
+ the watchdog will reset the system unless the watchdog reset is disabled.
+
+allOf:
+ - $ref: watchdog.yaml#
+
+properties:
+ compatible:
+ const: starfive,jh7110-wdt
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: APB clock
+ - description: Core clock
+
+ clock-names:
+ items:
+ - const: apb
+ - const: core
+
+ resets:
+ items:
+ - description: APB reset
+ - description: Core reset
+
+ reset-names:
+ items:
+ - const: apb
+ - const: core
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ watchdog@13070000 {
+ compatible = "starfive,jh7110-wdt";
+ reg = <0x13070000 0x10000>;
+ clocks = <&clk 122>,
+ <&clk 123>;
+ clock-names = "apb", "core";
+ resets = <&rst 109>,
+ <&rst 110>;
+ reset-names = "apb", "core";
+ };
Add bindings to describe the watchdog for the StarFive JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> --- .../watchdog/starfive,jh7110-wdt.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/starfive,jh7110-wdt.yaml