From patchwork Fri Feb 3 12:07:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 6590 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 05E2423E92 for ; Fri, 3 Feb 2012 12:07:40 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 98550A1832A for ; Fri, 3 Feb 2012 12:07:39 +0000 (UTC) Received: by iabz7 with SMTP id z7so6341365iab.11 for ; Fri, 03 Feb 2012 04:07:39 -0800 (PST) Received: by 10.42.177.133 with SMTP id bi5mr7691908icb.40.1328270858702; Fri, 03 Feb 2012 04:07:38 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.169.210 with SMTP id a18cs13370ibz; Fri, 3 Feb 2012 04:07:38 -0800 (PST) Received: by 10.213.27.74 with SMTP id h10mr2444355ebc.49.1328270856858; Fri, 03 Feb 2012 04:07:36 -0800 (PST) Received: from mail-ee0-f50.google.com (mail-ee0-f50.google.com [74.125.83.50]) by mx.google.com with ESMTPS id s4si3307253eeh.65.2012.02.03.04.07.36 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 03 Feb 2012 04:07:36 -0800 (PST) Received-SPF: neutral (google.com: 74.125.83.50 is neither permitted nor denied by best guess record for domain of daniel.lezcano@linaro.org) client-ip=74.125.83.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.83.50 is neither permitted nor denied by best guess record for domain of daniel.lezcano@linaro.org) smtp.mail=daniel.lezcano@linaro.org Received: by eeke53 with SMTP id e53so1135082eek.37 for ; Fri, 03 Feb 2012 04:07:36 -0800 (PST) Received: by 10.14.39.202 with SMTP id d50mr2221743eeb.79.1328270856187; Fri, 03 Feb 2012 04:07:36 -0800 (PST) Received: from localhost.localdomain (AToulouse-159-1-27-80.w92-134.abo.wanadoo.fr. [92.134.194.80]) by mx.google.com with ESMTPS id o49sm21176109eeb.7.2012.02.03.04.07.34 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 03 Feb 2012 04:07:35 -0800 (PST) From: Daniel Lezcano To: srinidhi.kasagar@stericsson.com, linus.walleij@stericsson.com Cc: linux-arm-kernel@lists.infradead.org, rickard.andersson@stericsson.com, jonas.aberg@stericsson.com, patches@linaro.org, linaro-dev@lists.linaro.org Subject: [PATCH] ux500 : decouple/recouple gic from the PRCMU Date: Fri, 3 Feb 2012 13:07:29 +0100 Message-Id: <1328270849-22324-1-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 1.7.5.4 This patch allows to decouple and recouple the gic from the PRCMU. This is needed to put the A9 core in retention mode with the cpuidle driver. Signed-off-by: Daniel Lezcano --- drivers/mfd/db8500-prcmu.c | 42 ++++++++++++++++++++++++++++++++++++++ include/linux/mfd/db8500-prcmu.h | 2 + include/linux/mfd/dbx500-prcmu.h | 16 ++++++++++++++ 3 files changed, 60 insertions(+), 0 deletions(-) diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index af8e0ef..c708431 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -528,6 +528,10 @@ static const char *hwacc_ret_regulator_name[NUM_HW_ACC] = { #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3 +#define PRCMU_A9_MASK_REQ 0x00000328 +#define PRCMU_A9_MASK_REQ_MASK 0x00000001 +#define PRCMU_A9_MASK_ACK 0x0000032C + static struct { u8 project_number; u8 api_version; @@ -787,6 +791,44 @@ int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) return 0; } +/* + * prcmu_gic_mask - apply the mask to the mask request + * register. This mask has the bits [1-31] reserved and + * the request applies to the bit 0 of this register. + */ +static inline void prcmu_gic_mask(u32 mask) +{ + u32 val = readl(_PRCMU_BASE + PRCMU_A9_MASK_REQ); + writel((val & ~PRCMU_A9_MASK_REQ_MASK) | mask, + _PRCMU_BASE + PRCMU_A9_MASK_REQ); +} + +/* + * db8500_prcmu_gic_disable - This function decouple the gic + * from the prcmu. + */ +void db8500_prcmu_gic_disable(void) +{ + prcmu_gic_mask(PRCMU_A9_MASK_REQ_MASK); + + /* Wait for gic mask register update */ + while (!(readl(_PRCMU_BASE + PRCMU_A9_MASK_REQ) & + PRCMU_A9_MASK_REQ_MASK)) + cpu_relax(); + + /* Wait a few cycles for the gic mask completion */ + udelay(1); +} + +/* + * db8500_prcmu_gic_enable - This function recouple the gic + * with the prcmu. + */ +void db8500_prcmu_gic_enable(void) +{ + prcmu_gic_mask(0); +} + /* This function should only be called while mb0_transfer.lock is held. */ static void config_wakeups(void) { diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h index 60d27f7..4a1032c 100644 --- a/include/linux/mfd/db8500-prcmu.h +++ b/include/linux/mfd/db8500-prcmu.h @@ -536,6 +536,8 @@ int prcmu_load_a9wdog(u8 id, u32 val); void db8500_prcmu_system_reset(u16 reset_code); int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll); +void db8500_prcmu_gic_disable(void); +void db8500_prcmu_gic_enable(void); void db8500_prcmu_enable_wakeups(u32 wakeups); int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state); int db8500_prcmu_request_clock(u8 clock, bool enable); diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h index bac942f..a5fee69 100644 --- a/include/linux/mfd/dbx500-prcmu.h +++ b/include/linux/mfd/dbx500-prcmu.h @@ -237,6 +237,22 @@ static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, keep_ap_pll); } +static inline void prcmu_gic_disable(void) +{ + if (machine_is_u5500()) + return; + else + return db8500_prcmu_gic_disable(); +} + +static inline void prcmu_gic_enable(void) +{ + if (machine_is_u5500()) + return; + else + return db8500_prcmu_gic_enable(); +} + static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) { if (machine_is_u5500())