[v3,1/7] dt-bindings: interconnect: qcom,msm8998-bwmon: Resolve MSM8998 support

BWMONv4 has two sets of registers: one for handling the monitor itself
and one called "global" which hosts some sort of a headswitch and an
interrupt control register. We did not handle that one before, as on
SoCs starting with SDM845 they have been merged into a single contiguous
range.

To make the qcom,msm8998-bwmon less confusing and in preparation for
actual MSM8998 support, describe the global register space and introduce
new "qcom,sdm845-cpu-bwmon" compatible while keeping the
"qcom,sdm845-bwmon" as a fallback for SoCs with this merged register space
scheme.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 .../bindings/interconnect/qcom,msm8998-bwmon.yaml  | 41 ++++++++++++++++++----
 1 file changed, 34 insertions(+), 7 deletions(-)

On Wed, Mar 15, 2023 at 03:11:19PM +0100, Konrad Dybcio wrote:
> BWMONv4 has two sets of registers: one for handling the monitor itself
> and one called "global" which hosts some sort of a headswitch and an
> interrupt control register. We did not handle that one before, as on
> SoCs starting with SDM845 they have been merged into a single contiguous
> range.
> 
> To make the qcom,msm8998-bwmon less confusing and in preparation for
> actual MSM8998 support, describe the global register space and introduce
> new "qcom,sdm845-cpu-bwmon" compatible while keeping the
> "qcom,sdm845-bwmon" as a fallback for SoCs with this merged register space
> scheme.
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Georgi, can you please pick this patch through your tree?

Regards,
Bjorn

> ---
>  .../bindings/interconnect/qcom,msm8998-bwmon.yaml  | 41 ++++++++++++++++++----
>  1 file changed, 34 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
> index 12a0d3ecbabb..5d17bdcfdf70 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
> @@ -22,14 +22,14 @@ description: |
>  properties:
>    compatible:
>      oneOf:
> +      - const: qcom,msm8998-bwmon       # BWMON v4
>        - items:
>            - enum:
>                - qcom,sc7280-cpu-bwmon
>                - qcom,sc8280xp-cpu-bwmon
> -              - qcom,sdm845-bwmon
> +              - qcom,sdm845-cpu-bwmon
>                - qcom,sm8550-cpu-bwmon
> -          - const: qcom,msm8998-bwmon
> -      - const: qcom,msm8998-bwmon       # BWMON v4
> +          - const: qcom,sdm845-bwmon    # BWMON v4, unified register space
>        - items:
>            - enum:
>                - qcom,sc8280xp-llcc-bwmon
> @@ -49,9 +49,13 @@ properties:
>      type: object
>  
>    reg:
> -    # BWMON v4 (currently described) and BWMON v5 use one register address
> -    # space.  BWMON v2 uses two register spaces - not yet described.
> -    maxItems: 1
> +    # BWMON v5 uses one register address space, v1-v4 use one or two.
> +    minItems: 1
> +    maxItems: 2
> +
> +  reg-names:
> +    minItems: 1
> +    maxItems: 2
>  
>  required:
>    - compatible
> @@ -63,13 +67,36 @@ required:
>  
>  additionalProperties: false
>  
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          const: qcom,msm8998-bwmon
> +    then:
> +      properties:
> +        reg:
> +          minItems: 2
> +
> +        reg-names:
> +          items:
> +            - const: monitor
> +            - const: global
> +
> +    else:
> +      properties:
> +        reg:
> +          maxItems: 1
> +
> +        reg-names:
> +          maxItems: 1
> +
>  examples:
>    - |
>      #include <dt-bindings/interconnect/qcom,sdm845.h>
>      #include <dt-bindings/interrupt-controller/arm-gic.h>
>  
>      pmu@1436400 {
> -        compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon";
> +        compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
>          reg = <0x01436400 0x600>;
>          interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
>          interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
> 
> -- 
> 2.39.2
>

On 4.04.23 22:35, Bjorn Andersson wrote:
> On Wed, Mar 15, 2023 at 03:11:19PM +0100, Konrad Dybcio wrote:
>> BWMONv4 has two sets of registers: one for handling the monitor itself
>> and one called "global" which hosts some sort of a headswitch and an
>> interrupt control register. We did not handle that one before, as on
>> SoCs starting with SDM845 they have been merged into a single contiguous
>> range.
>>
>> To make the qcom,msm8998-bwmon less confusing and in preparation for
>> actual MSM8998 support, describe the global register space and introduce
>> new "qcom,sdm845-cpu-bwmon" compatible while keeping the
>> "qcom,sdm845-bwmon" as a fallback for SoCs with this merged register space
>> scheme.
>>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> 
> Georgi, can you please pick this patch through your tree?

Yes, sure!

BR,
Georgi

> Regards,
> Bjorn
> 
>> ---
>>   .../bindings/interconnect/qcom,msm8998-bwmon.yaml  | 41 ++++++++++++++++++----
>>   1 file changed, 34 insertions(+), 7 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
>> index 12a0d3ecbabb..5d17bdcfdf70 100644
>> --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
>> @@ -22,14 +22,14 @@ description: |
>>   properties:
>>     compatible:
>>       oneOf:
>> +      - const: qcom,msm8998-bwmon       # BWMON v4
>>         - items:
>>             - enum:
>>                 - qcom,sc7280-cpu-bwmon
>>                 - qcom,sc8280xp-cpu-bwmon
>> -              - qcom,sdm845-bwmon
>> +              - qcom,sdm845-cpu-bwmon
>>                 - qcom,sm8550-cpu-bwmon
>> -          - const: qcom,msm8998-bwmon
>> -      - const: qcom,msm8998-bwmon       # BWMON v4
>> +          - const: qcom,sdm845-bwmon    # BWMON v4, unified register space
>>         - items:
>>             - enum:
>>                 - qcom,sc8280xp-llcc-bwmon
>> @@ -49,9 +49,13 @@ properties:
>>       type: object
>>   
>>     reg:
>> -    # BWMON v4 (currently described) and BWMON v5 use one register address
>> -    # space.  BWMON v2 uses two register spaces - not yet described.
>> -    maxItems: 1
>> +    # BWMON v5 uses one register address space, v1-v4 use one or two.
>> +    minItems: 1
>> +    maxItems: 2
>> +
>> +  reg-names:
>> +    minItems: 1
>> +    maxItems: 2
>>   
>>   required:
>>     - compatible
>> @@ -63,13 +67,36 @@ required:
>>   
>>   additionalProperties: false
>>   
>> +allOf:
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          const: qcom,msm8998-bwmon
>> +    then:
>> +      properties:
>> +        reg:
>> +          minItems: 2
>> +
>> +        reg-names:
>> +          items:
>> +            - const: monitor
>> +            - const: global
>> +
>> +    else:
>> +      properties:
>> +        reg:
>> +          maxItems: 1
>> +
>> +        reg-names:
>> +          maxItems: 1
>> +
>>   examples:
>>     - |
>>       #include <dt-bindings/interconnect/qcom,sdm845.h>
>>       #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   
>>       pmu@1436400 {
>> -        compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon";
>> +        compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
>>           reg = <0x01436400 0x600>;
>>           interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
>>           interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
>>
>> -- 
>> 2.39.2
>>