diff mbox series

[3/3] armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is present

Message ID 20230317162253.1049446-4-paul.liu@linaro.org
State New
Headers show
Series Use FEAT_HAFDBS to track dirty pages | expand

Commit Message

Paul Liu March 17, 2023, 4:22 p.m. UTC 
From: meitao <meitaogao@asrmicro.com>

u-boot could be run at EL1/EL2/EL3. so we set it as same as EL1 does.
otherwise it will hang when enable mmu, that is what we encounter
in our SOC.

Signed-off-by: meitao <meitaogao@asrmicro.com>
[ Paul: pick from the Android tree. Rebase to the upstream ]
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Link: https://android.googlesource.com/platform/external/u-boot/+/3bf38943aeab4700c2319bff2a1477d99c6afd2f
---
 arch/arm/cpu/armv8/cache_v8.c    |  6 +++++-
 arch/arm/include/asm/armv8/mmu.h | 10 ++++++++--
 2 files changed, 13 insertions(+), 3 deletions(-)

Comments

Tom Rini April 26, 2023, 12:30 p.m. UTC | #1 
On Sat, Mar 18, 2023 at 12:22:53AM +0800, Ying-Chun Liu (PaulLiu) wrote:

> From: meitao <meitaogao@asrmicro.com>
> 
> u-boot could be run at EL1/EL2/EL3. so we set it as same as EL1 does.
> otherwise it will hang when enable mmu, that is what we encounter
> in our SOC.
> 
> Signed-off-by: meitao <meitaogao@asrmicro.com>
> [ Paul: pick from the Android tree. Rebase to the upstream ]
> Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
> Cc: Tom Rini <trini@konsulko.com>
> Link: https://android.googlesource.com/platform/external/u-boot/+/3bf38943aeab4700c2319bff2a1477d99c6afd2f

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 4c6a1b1d6c..cb1131a048 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -94,11 +94,15 @@  u64 get_tcr(u64 *pips, u64 *pva_bits)
 	if (el == 1) {
 		tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
 		if (gd->arch.has_hafdbs)
-			tcr |= TCR_HA | TCR_HD;
+			tcr |= TCR_EL1_HA | TCR_EL1_HD;
 	} else if (el == 2) {
 		tcr = TCR_EL2_RSVD | (ips << 16);
+		if (gd->arch.has_hafdbs)
+			tcr |= TCR_EL2_HA | TCR_EL2_HD;
 	} else {
 		tcr = TCR_EL3_RSVD | (ips << 16);
+		if (gd->arch.has_hafdbs)
+			tcr |= TCR_EL3_HA | TCR_EL3_HD;
 	}
 
 	/* PTWs cacheable, inner/outer WBWA and inner shareable */
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 98a27db316..19a9e112a4 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -102,8 +102,14 @@ 
 #define TCR_TG0_16K		(2 << 14)
 #define TCR_EPD1_DISABLE	(1 << 23)
 
-#define TCR_HA			BIT(39)
-#define TCR_HD			BIT(40)
+#define TCR_EL1_HA		BIT(39)
+#define TCR_EL1_HD		BIT(40)
+
+#define TCR_EL2_HA		BIT(21)
+#define TCR_EL2_HD		BIT(22)
+
+#define TCR_EL3_HA		BIT(21)
+#define TCR_EL3_HD		BIT(22)
 
 #define TCR_EL1_RSVD		(1U << 31)
 #define TCR_EL2_RSVD		(1U << 31 | 1 << 23)