@@ -10,17 +10,55 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+
#include "fsl-ls1088a.dtsi"
/ {
model = "LS1088A RDB Board";
compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
+
+ clk_100mhz: clock-100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_156mhz: clock-156mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <156250000>;
+ };
+
+ sfp_slot: sfp {
+ compatible = "sff,sfp";
+ i2c-bus = <&sfp_i2c>;
+ los-gpios = <&los_stat 5 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&los_stat 4 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&brdcfg9 4 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&serdes1 {
+ clocks = <&clk_100mhz>, <&clk_156mhz>;
+ clock-names = "ref0", "ref1";
+ fsl,unused-lanes-reserved;
+ status = "okay";
+};
+
+&dpmac1 {
+ managed = "in-band-status";
+ pcs-handle = <&pcs1>;
+ phys = <&serdes1_C>;
+ sfp = <&sfp_slot>;
};
&dpmac2 {
phy-handle = <&mdio2_aquantia_phy>;
phy-connection-type = "10gbase-r";
+ managed = "in-band-status";
pcs-handle = <&pcs2>;
+ phys = <&serdes1_D>;
};
&dpmac3 {
@@ -28,6 +66,7 @@ &dpmac3 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_0>;
+ phys = <&serdes1_A>;
};
&dpmac4 {
@@ -35,6 +74,7 @@ &dpmac4 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_1>;
+ phys = <&serdes1_A>;
};
&dpmac5 {
@@ -42,6 +82,7 @@ &dpmac5 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_2>;
+ phys = <&serdes1_A>;
};
&dpmac6 {
@@ -49,6 +90,7 @@ &dpmac6 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_3>;
+ phys = <&serdes1_A>;
};
&dpmac7 {
@@ -56,6 +98,7 @@ &dpmac7 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_0>;
+ phys = <&serdes1_B>;
};
&dpmac8 {
@@ -63,6 +106,7 @@ &dpmac8 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_1>;
+ phys = <&serdes1_B>;
};
&dpmac9 {
@@ -70,6 +114,7 @@ &dpmac9 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_2>;
+ phys = <&serdes1_B>;
};
&dpmac10 {
@@ -77,6 +122,7 @@ &dpmac10 {
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs7_3>;
+ phys = <&serdes1_B>;
};
&emdio1 {
@@ -128,7 +174,6 @@ &emdio2 {
mdio2_aquantia_phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
- interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
reg = <0x0>;
};
};
@@ -171,6 +216,12 @@ rtc@51 {
interrupts-extended = <&extirq 0 IRQ_TYPE_LEVEL_LOW>;
};
};
+
+ sfp_i2c: i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6>;
+ };
};
};
@@ -185,8 +236,31 @@ nand@0,0 {
};
fpga: board-control@2,0 {
- compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis",
+ "simple-bus";
reg = <0x2 0x0 0x0000100>;
+ ranges = <0x0 0x2 0x0 0x0000100>;
+
+ los_stat: gpio-controller@1d {
+ #gpio-cells = <2>;
+ compatible = "fsl,fpga-qixis-los-stat",
+ "ni,169445-nand-gpio";
+ reg = <0x1d 0x1>;
+ reg-names = "dat";
+ gpio-controller;
+ no-output;
+ };
+
+ brdcfg9: gpio-controller@59 {
+ #gpio-cells = <2>;
+ compatible = "fsl,fpga-qixis-brdcfg9",
+ "ni,169445-nand-gpio";
+ reg = <0x59 0x1>;
+ reg-names = "dat";
+ gpio-controller;
+ };
};
};
@@ -203,6 +277,10 @@ &esdhc {
status = "okay";
};
+&pcs_mdio1 {
+ status = "okay";
+};
+
&pcs_mdio2 {
status = "okay";
};
This adds serdes support to the LS1088ARDB. I have tested the QSGMII ports as well as the two 10G ports. The SFP slot is now fully supported, instead of being modeled as a fixed-link. Linux hangs around when the serdes is initialized if the si5341 is enabled with the in-tree driver, so I have modeled it as a two fixed clocks instead. There are a few registers in the QIXIS FPGA which control the SFP GPIOs; I have modeled them as discrete GPIO controllers for now. I never saw the AQR105 interrupt fire; not sure what was going on, but I have removed it to force polling. To enable serdes support, the DPC needs to set the macs to MAC_LINK_TYPE_BACKPLANE. All MACs using the same QSGMII should be converted at once. Additionally, in order to change interface types, the MC firmware must support DPAA2_MAC_FEATURE_PROTOCOL_CHANGE. Signed-off-by: Sean Anderson <sean.anderson@seco.com> --- (no changes since v10) Changes in v10: - Move serdes bindings to SoC dtsi - Use "descriptions" instead of "bindings" - Don't use /clocks - Add missing gpio-controller properties Changes in v9: - Add fsl,unused-lanes-reserved to allow a gradual transition, depending on the mac link type. - Remove unused clocks - Fix some phy mode node names - phy-type -> fsl,phy Changes in v8: - Rename serdes phy handles like the LS1046A - Add SFP slot binding - Fix incorrect lane ordering (it's backwards on the LS1088A just like it is in the LS1046A). - Fix duplicated lane 2 (it should have been lane 3). - Fix incorrectly-documented value for XFI1. - Remove interrupt for aquantia phy. It never fired for whatever reason, preventing the link from coming up. - Add GPIOs for QIXIS FPGA. - Enable MAC1 PCS - Remove si5341 binding Changes in v4: - Convert to new bindings .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 82 ++++++++++++++++++- 1 file changed, 80 insertions(+), 2 deletions(-)