| Message ID | 20230323233735.2131020-6-vladimir.zapolskiy@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: qcom: add QCE on SM8250 and SM8450 platforms | expand |
On Fri, 24 Mar 2023 at 05:07, Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> wrote: > > Add description of QCE and its corresponding BAM DMA IPs on SM8450 SoC. > > Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index ce4b7d0a09ab..228c26fb9003 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -4081,6 +4081,28 @@ ufs_mem_phy_lanes: phy@1d87400 { > }; > }; > > + cryptobam: dma-controller@1dc4000 { > + compatible = "qcom,bam-v1.7.0"; > + reg = <0x0 0x01dc4000 0x0 0x24000>; > + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; > + #dma-cells = <1>; > + qcom,ee = <0>; > + qcom,controlled-remotely; > + num-channels = <8>; > + qcom,num-ees = <2>; > + iommus = <&apps_smmu 0x584 0x11>; > + }; > + > + crypto: crypto@1dfa000 { > + compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; > + reg = <0x0 0x01dfa000 0x0 0x6000>; > + dmas = <&cryptobam 4>, <&cryptobam 5>; > + dma-names = "rx", "tx"; > + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "memory"; > + iommus = <&apps_smmu 0x584 0x11>; > + }; > + > sdhc_2: mmc@8804000 { > compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; > reg = <0 0x08804000 0 0x1000>; > -- > 2.33.0 Already folded Neil's patch and sent via [1], which includes the correct BAM DMA compatible list as well. [1]. https://lore.kernel.org/linux-arm-msm/20230322114519.3412469-11-bhupesh.sharma@linaro.org/ Thanks.
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index ce4b7d0a09ab..228c26fb9003 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4081,6 +4081,28 @@ ufs_mem_phy_lanes: phy@1d87400 { }; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x24000>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <8>; + qcom,num-ees = <2>; + iommus = <&apps_smmu 0x584 0x11>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "memory"; + iommus = <&apps_smmu 0x584 0x11>; + }; + sdhc_2: mmc@8804000 { compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>;
Add description of QCE and its corresponding BAM DMA IPs on SM8450 SoC. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)