| Message ID | 1679551448-19160-11-git-send-email-quic_taozha@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support to configure TPDM DSB subunit | expand |
On 23/03/2023 06:04, Tao Zhang wrote: > Add property "qcom,dsb_msr_num" to support DSB(Discrete Single > Bit) MSR(mux select register) for TPDM. It specifies the number > of MSR registers supported by the DSB TDPM. > > Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> > --- > Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > index d9b6b613..691c7ba 100644 > --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > @@ -53,6 +53,15 @@ properties: > minimum: 32 > maximum: 64 > > + qcom,dsb_msr_num: nit: "qcom,dsb-msr-num" ? or even "qcom,dsb-num-msrs" ? Suzuki
On 23/03/2023 07:04, Tao Zhang wrote: > Add property "qcom,dsb_msr_num" to support DSB(Discrete Single > Bit) MSR(mux select register) for TPDM. It specifies the number > of MSR registers supported by the DSB TDPM. > > Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> > --- > Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > index d9b6b613..691c7ba 100644 > --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml > @@ -53,6 +53,15 @@ properties: > minimum: 32 > maximum: 64 > > + qcom,dsb_msr_num: Underscores are not allowed. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index d9b6b613..691c7ba 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -53,6 +53,15 @@ properties: minimum: 32 maximum: 64 + qcom,dsb_msr_num: + description: + Specifies the number of DSB(Discrete Single Bit) MSR(mux select register) + registers supported by the monitor. If this property is not configured + or set to 0, it means this DSB TPDM doesn't support MSR. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 32 + clocks: maxItems: 1 @@ -87,6 +96,7 @@ examples: reg = <0x0684c000 0x1000>; qcom,dsb-element-size = <32>; + qcom,dsb_msr_num = <16>; clocks = <&aoss_qmp>; clock-names = "apb_pclk";
Add property "qcom,dsb_msr_num" to support DSB(Discrete Single Bit) MSR(mux select register) for TPDM. It specifies the number of MSR registers supported by the DSB TDPM. Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> --- Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+)