diff mbox series

[3/5] reset: qcom: Add support for SM6115 SoC reset table

Message ID 20230324080418.3856409-4-bhupesh.sharma@linaro.org
State New
Headers show
Series New boards support: Qualcomm RB2 board | expand

Commit Message

Bhupesh Sharma March 24, 2023, 8:04 a.m. UTC 
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 drivers/reset/reset-qcom.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
diff mbox series

Patch

diff --git a/drivers/reset/reset-qcom.c b/drivers/reset/reset-qcom.c
index 94315e76d5..046d2c083b 100644
--- a/drivers/reset/reset-qcom.c
+++ b/drivers/reset/reset-qcom.c
@@ -131,6 +131,24 @@  static const struct qcom_reset_map gcc_qcom_resets[] = {
 };
 #endif
 
+#ifdef CONFIG_TARGET_QRB4210RB2
+#include <dt-bindings/clock/qcom,gcc-sm6115.h>
+static const struct qcom_reset_map gcc_qcom_resets[] = {
+	[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
+	[GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
+	[GCC_SDCC1_BCR] = { 0x38000 },
+	[GCC_SDCC2_BCR] = { 0x1e000 },
+	[GCC_UFS_PHY_BCR] = { 0x45000 },
+	[GCC_USB30_PRIM_BCR] = { 0x1a000 },
+	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
+	[GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
+	[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
+	[GCC_VCODEC0_BCR] = { 0x58094 },
+	[GCC_VENUS_BCR] = { 0x58078 },
+	[GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
+};
+#endif
+
 static int qcom_reset_assert(struct reset_ctl *rst)
 {
 	struct qcom_reset_priv *priv = dev_get_priv(rst->dev);