@@ -47,3 +47,4 @@ stable hypervisors.
| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
| ARM | Cortex-A57 | #852523 | N/A |
| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
+| ARM | Cortex-A57 | #834220 | N/A |
@@ -2396,6 +2396,21 @@ static void do_trap_instr_abort_guest(struct cpu_user_regs *regs,
.kind = hsr.iabt.s1ptw ? npfec_kind_in_gpt : npfec_kind_with_gla
};
+ /*
+ * Erratum #834220: The processor may report a Stage 2
+ * translation fault as the result of Stage 1 fault for load
+ * crossing a page boundary when there is a permission fault or
+ * device memory alignment fault at Stage 1 and a translation
+ * fault at Stage 2.
+ *
+ * So Xen needs to check that the Stage 1 translation does not
+ * generate a fault before handling stage 2 fault. If it is a Stage
+ * 1 translation fault, return to the guest to let the processor
+ * injecting the correct fault.
+ *
+ * XXX: This can be optimized to avoid some unecessary
+ * translation.
+ */
if ( hsr.iabt.s1ptw )
gpa = get_faulting_ipa();
else
@@ -2445,6 +2460,21 @@ static void do_trap_data_abort_guest(struct cpu_user_regs *regs,
info.gva = READ_SYSREG64(FAR_EL2);
#endif
+ /*
+ * Erratum #834220: The processor may report a Stage 2
+ * translation fault as the result of Stage 1 fault for load
+ * crossing a page boundary when there is a permission fault or
+ * device memory alignment fault at Stage 1 and a translation
+ * fault at Stage 2.
+ *
+ * So Xen needs to check that the Stage 1 translation does not
+ * generate a fault before handling stage 2 fault. If it is a Stage
+ * 1 translation fault, return to the guest to let the processor
+ * injecting the correct fault.
+ *
+ * XXX: This can be optimized to avoid some unecessary
+ * translation.
+ */
if ( dabt.s1ptw )
info.gpa = get_faulting_ipa();
else
The ARM erratum applies to certain revisions of Cortex-A57. The processor may report a Stage 2 translation fault as the result of Stage 1 fault for load crossing a page boundary when there is a permission fault or device memory fault at stage 1 and a translation fault at Stage 2. So Xen needs to check that Stage 1 translation does not generate a fault before handling the Stage 2 fault. If it is a Stage 1 translation fault, return to the guest to let the processor injecting the correct fault. Only document it as this is already the behavior of the fault handlers. Note that some optimization could be done to avoid unecessary translation fault. This is because HPFAR_EL2 is valid for more use case. For the moment, the code is left unmodified. Signed-off-by: Julien Grall <julien.grall@arm.com> --- docs/misc/arm/silicon-errata.txt | 1 + xen/arch/arm/traps.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+)