| Message ID | 1462544971-7875-1-git-send-email-ard.biesheuvel@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
On Fri, May 06, 2016 at 04:29:31PM +0200, Ard Biesheuvel wrote: > The pre-v3.0 SMBIOS entry point only has a 32-bit field to store the > address of the structure table, and so it does not make sense to attempt > to generate such an entry point if you don't have any RAM below 4 GB. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Looks good, thanks. Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> > --- > Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 2 ++ > Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc > index 581a2e02f9b8..892068f62025 100644 > --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc > +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc > @@ -507,6 +507,8 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) > gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE > gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE > > + # SMBIOS 3.0 only > + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 > > [PcdsDynamicDefault.common] > gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES) > diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc > index 16b6f5469ca7..32d97c017b46 100644 > --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc > +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc > @@ -519,6 +519,8 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) > gAmdStyxTokenSpaceGuid.PcdIscpSupport|FALSE > !endif > > + # SMBIOS 3.0 only > + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 > > [PcdsDynamicDefault.common] > gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES) > -- > 2.7.4 >
diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc index 581a2e02f9b8..892068f62025 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -507,6 +507,8 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE + # SMBIOS 3.0 only + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 [PcdsDynamicDefault.common] gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES) diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index 16b6f5469ca7..32d97c017b46 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -519,6 +519,8 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gAmdStyxTokenSpaceGuid.PcdIscpSupport|FALSE !endif + # SMBIOS 3.0 only + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 [PcdsDynamicDefault.common] gAmdStyxTokenSpaceGuid.PcdSocCoreCount|$(NUM_CORES)
The pre-v3.0 SMBIOS entry point only has a 32-bit field to store the address of the structure table, and so it does not make sense to attempt to generate such an entry point if you don't have any RAM below 4 GB. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 2 ++ Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 2 ++ 2 files changed, 4 insertions(+)