From patchwork Wed May 11 16:00:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 67604 Delivered-To: patch@linaro.org Received: by 10.140.92.199 with SMTP id b65csp310597qge; Wed, 11 May 2016 09:19:49 -0700 (PDT) X-Received: by 10.140.98.38 with SMTP id n35mr4396015qge.22.1462983589470; Wed, 11 May 2016 09:19:49 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id 41si5718293qgh.1.2016.05.11.09.19.49; Wed, 11 May 2016 09:19:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 1BF9961647; Wed, 11 May 2016 16:19:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 442346166C; Wed, 11 May 2016 16:05:31 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 3579C6166C; Wed, 11 May 2016 16:05:27 +0000 (UTC) Received: from mail-wm0-f54.google.com (mail-wm0-f54.google.com [74.125.82.54]) by lists.linaro.org (Postfix) with ESMTPS id 323FE6166C for ; Wed, 11 May 2016 16:01:29 +0000 (UTC) Received: by mail-wm0-f54.google.com with SMTP id g17so90867457wme.1 for ; Wed, 11 May 2016 09:01:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cW3APDx3K6E2L94R1Nr78YTf9iQSwq9fyI8UxPkphOs=; b=TnTpEziwDZpznJ+nZJp+yhz6Zt4fyAOqwM33HmxKhJ0N0uZw6AyBjeEke4Tj429qxH cM8fy25SIT66VDcTO285gBEnJ3qSXVo2doSZnDCW+Rxwqm975LL9b0VPdehcMUcuACWj pPesePvhVJNadp/MSabizEkHVxsZdNzLTgVpIk2wTMyCSQIVM/uM475GC2T6QKWMJnuA QGJpIJpaqwrI+h51D0ObvTFajrfqqgFKqECV1IcPl73szLNbNUDFylsnPW7+NHKt+eKm oOuU0mzsluMN79miBeGRR4u/523A+kKge4dlTDGiz1sMDveb7HkTYxi3U2O543wl3Su1 ALmA== X-Gm-Message-State: AOPr4FXXBQUZMMonVE4pshgue/lDep9MR0831bfCDkXWFbPJQfgKFteUexnKQVovekMqRGagcXw= X-Received: by 10.194.95.40 with SMTP id dh8mr4987161wjb.146.1462982488335; Wed, 11 May 2016 09:01:28 -0700 (PDT) Received: from localhost.localdomain ([195.55.142.58]) by smtp.gmail.com with ESMTPSA id f11sm36699133wmf.22.2016.05.11.09.01.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 May 2016 09:01:27 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Wed, 11 May 2016 18:00:50 +0200 Message-Id: <1462982452-1316-10-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1462982452-1316-1-git-send-email-ard.biesheuvel@linaro.org> References: <1462982452-1316-1-git-send-email-ard.biesheuvel@linaro.org> Cc: leo.duran@amd.com Subject: [Linaro-uefi] [PATCH 09/11] Platforms/AMD/Styx: DSC spring cleaning X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Remove options that are no longer used. Note that the vendor string is now set via a different PCD, making it visible to the OS via the system table. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 60 +------------------- Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 57 +------------------ 2 files changed, 2 insertions(+), 115 deletions(-) diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc index 13ddbabe2a11..345f04a25e3e 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -21,10 +21,6 @@ DEFINE NUM_CORES = 8 DEFINE DO_KCS = 0 DEFINE DO_RTK = 0 -DEFINE EL3_TO_EL1 = 0x3C5 -DEFINE EL3_TO_EL2 = 0x3C9 -DEFINE TRANS_CODE = $(EL3_TO_EL2) - PLATFORM_NAME = Cello PLATFORM_GUID = 77861b3e-74b0-4ff3-8d18-c5ba5803e1bf PLATFORM_VERSION = 0.1 @@ -94,7 +90,6 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) # ARM Architectural Libraries CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf -# CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf @@ -284,20 +279,7 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE - gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|FALSE - # - # Control what commands are supported from the UI - # Turn these on and off to add features or save size - # - gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE - gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE - gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE - gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE - gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE - gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE - gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE - # All pages are cached by default gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE @@ -356,10 +338,6 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 - gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|"" - gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07 - gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000 - # # Optional feature to help prevent EFI memory map fragments # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob @@ -380,38 +358,20 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 - # - # ARM Pcds - # - gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000 - gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } - gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"AMD Seattle" - gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"Seattle" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"AMD Seattle" # Number of configured cores gArmPlatformTokenSpaceGuid.PcdCoreCount|$(NUM_CORES) - # Enable floating point - gArmTokenSpaceGuid.PcdVFPEnabled|1 - # Stacks for MPCores in Normal World gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x8001680000 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800 - # Stacks for MPCores in Monitor Mode - gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x8001688000 - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100 - - # Stacks for MPCores in Secure World - gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x8001689000 - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000 - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x800 - # Declare system memory base gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000000000 @@ -419,21 +379,6 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000 # - # ARM Pcds - # - gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000 - - # Trustzone enable - # (to make the transition from EL3 to EL2 in ArmPlatformPkg/Sec) - gArmTokenSpaceGuid.PcdTrustzoneSupport|TRUE - - # Secure Configuration Register - gArmTokenSpaceGuid.PcdArmScr|0x531 - - # EL Transition Code - gArmTokenSpaceGuid.PcdArmNonSecModeTransition|$(TRANS_CODE) - - # # ARM PrimeCell # @@ -484,9 +429,6 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gArmTokenSpaceGuid.PcdPciMmio64Size|0x7F00000000 gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0 - ## Use PCI emulation for ATA PassThru - # gEfiMdeModulePkgTokenSpaceGuid.PcdAtaPassThruPciEmulation|TRUE - ## ACPI (no tables < 4GB) gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index 5a6f74f48162..b5069b073d45 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -24,10 +24,6 @@ DEFINE DO_ISCP = 1 DEFINE DO_KCS = 1 DEFINE DO_RTK = 0 -DEFINE EL3_TO_EL1 = 0x3C5 -DEFINE EL3_TO_EL2 = 0x3C9 -DEFINE TRANS_CODE = $(EL3_TO_EL2) - PLATFORM_NAME = Overdrive PLATFORM_GUID = B2296C02-9DA1-4CD1-BD48-4D4F0F1276EB PLATFORM_VERSION = 0.1 @@ -97,7 +93,6 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) # ARM Architectural Libraries CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf -# CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf @@ -291,20 +286,7 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE - gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|FALSE - # - # Control what commands are supported from the UI - # Turn these on and off to add features or save size - # - gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE - gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE - gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE - gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE - gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE - gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE - gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE - # All pages are cached by default gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE @@ -363,10 +345,6 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 - gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|"" - gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07 - gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000 - # # Optional feature to help prevent EFI memory map fragments # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob @@ -387,38 +365,20 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 - # - # ARM Pcds - # - gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000 - gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } - gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"AMD Seattle" - gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"Seattle" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"AMD Seattle" # Number of configured cores gArmPlatformTokenSpaceGuid.PcdCoreCount|$(NUM_CORES) - # Enable floating point - gArmTokenSpaceGuid.PcdVFPEnabled|1 - # Stacks for MPCores in Normal World gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x8001680000 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x800 - # Stacks for MPCores in Monitor Mode - gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x8001688000 - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100 - - # Stacks for MPCores in Secure World - gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x8001689000 - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000 - gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x800 - # Declare system memory base gArmTokenSpaceGuid.PcdSystemMemoryBase|0x8000000000 @@ -426,21 +386,6 @@ DEFINE TRANS_CODE = $(EL3_TO_EL2) gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000 # - # ARM Pcds - # - gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000 - - # Trustzone enable - # (to make the transition from EL3 to EL2 in ArmPlatformPkg/Sec) - gArmTokenSpaceGuid.PcdTrustzoneSupport|TRUE - - # Secure Configuration Register - gArmTokenSpaceGuid.PcdArmScr|0x531 - - # EL Transition Code - gArmTokenSpaceGuid.PcdArmNonSecModeTransition|$(TRANS_CODE) - - # # ARM PrimeCell #