| Message ID | 1682338412-15420-3-git-send-email-mantas@8devices.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/3] clk: qcom: gcc-ipq6018: Use floor ops for sdcc clocks | expand |
On 24. 04. 2023. 14:13, Mantas Pucka wrote: > IPQ6018 has one SD/eMMC controller, add node for it. > > Signed-off-by: Mantas Pucka <mantas@8devices.com> Tested-by: Robert Marko <robimarko@gmail.com> > --- > arch/arm64/boot/dts/qcom/ipq6018.dtsi | 23 +++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > index 9ff4e9d45065..b129b23d68b1 100644 > --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > @@ -414,6 +414,29 @@ > }; > }; > > + sdhc_1: mmc@7804000 { > + compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0x0 0x07804000 0x0 0x1000>, > + <0x0 0x07805000 0x0 0x1000>, > + <0x0 0x07808000 0x0 0x2000>; > + reg-names = "hc", "cqhci", "ice"; > + > + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hc_irq", "pwr_irq"; > + > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > + <&gcc GCC_SDCC1_APPS_CLK>, > + <&xo>, > + <&gcc GCC_SDCC1_ICE_CORE_CLK>; > + clock-names = "iface", "core", "xo", "ice"; > + > + resets = <&gcc GCC_SDCC1_BCR>; > + supports-cqe; > + bus-width = <8>; > + status = "disabled"; > + }; > + > blsp_dma: dma-controller@7884000 { > compatible = "qcom,bam-v1.7.0"; > reg = <0x0 0x07884000 0x0 0x2b000>;
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 9ff4e9d45065..b129b23d68b1 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -414,6 +414,29 @@ }; }; + sdhc_1: mmc@7804000 { + compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x07804000 0x0 0x1000>, + <0x0 0x07805000 0x0 0x1000>, + <0x0 0x07808000 0x0 0x2000>; + reg-names = "hc", "cqhci", "ice"; + + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "xo", "ice"; + + resets = <&gcc GCC_SDCC1_BCR>; + supports-cqe; + bus-width = <8>; + status = "disabled"; + }; + blsp_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x07884000 0x0 0x2b000>;
IPQ6018 has one SD/eMMC controller, add node for it. Signed-off-by: Mantas Pucka <mantas@8devices.com> --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)