From patchwork Sat Mar 19 03:00:02 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Pitre X-Patchwork-Id: 678 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:44:39 -0000 Delivered-To: patches@linaro.org Received: by 10.220.28.198 with SMTP id n6cs49430vcc; Fri, 18 Mar 2011 20:00:06 -0700 (PDT) Received: by 10.52.0.231 with SMTP id 7mr1940488vdh.154.1300503605374; Fri, 18 Mar 2011 20:00:05 -0700 (PDT) Received: from relais.videotron.ca (relais.videotron.ca [24.201.245.36]) by mx.google.com with ESMTP id n9si3997875vcr.200.2011.03.18.20.00.02; Fri, 18 Mar 2011 20:00:04 -0700 (PDT) Received-SPF: neutral (google.com: 24.201.245.36 is neither permitted nor denied by best guess record for domain of nico@fluxnic.net) client-ip=24.201.245.36; Authentication-Results: mx.google.com; spf=neutral (google.com: 24.201.245.36 is neither permitted nor denied by best guess record for domain of nico@fluxnic.net) smtp.mail=nico@fluxnic.net MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: TEXT/PLAIN; charset=US-ASCII Received: from xanadu.home ([66.130.28.92]) by vl-mh-mrz25.ip.videotron.ca (Sun Java(tm) System Messaging Server 6.3-8.01 (built Dec 16 2008; 32bit)) with ESMTP id <0LIA00MBLAXSEX00@vl-mh-mrz25.ip.videotron.ca> for patches@linaro.org; Fri, 18 Mar 2011 22:58:40 -0400 (EDT) Date: Fri, 18 Mar 2011 23:00:02 -0400 (EDT) From: Nicolas Pitre X-X-Sender: nico@xanadu.home To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org Subject: [PATCH] ARM: kernel/sleep.S: fix Thumb2 compilation issues Message-id: User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) Signed-off-by: Nicolas Pitre Reviewed-by: Dave Martin diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S index bfad698..6398ead 100644 --- a/arch/arm/kernel/sleep.S +++ b/arch/arm/kernel/sleep.S @@ -119,11 +119,19 @@ ENTRY(cpu_resume) #else ldr r0, sleep_save_sp @ stack phys addr #endif - msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off + setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off #ifdef MULTI_CPU - ldmia r0!, {r1, sp, lr, pc} @ load v:p, stack, return fn, resume fn + @ load v:p, stack, return fn, resume fn + ARM( ldmia r0!, {r1, sp, lr, pc} ) +THUMB( ldmia r0!, {r1, r2, r3, r4} ) +THUMB( mov sp, r2 ) +THUMB( mov lr, r3 ) +THUMB( bx r4 ) #else - ldmia r0!, {r1, sp, lr} @ load v:p, stack, return fn + @ load v:p, stack, return fn + ARM( ldmia r0!, {r1, sp, lr} ) +THUMB( ldmia r0!, {r1, r2, lr} ) +THUMB( mov sp, r2 ) b cpu_do_resume #endif ENDPROC(cpu_resume)