| Message ID | 20230427123314.1997152-5-joychakr@google.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | spi: dw: DW SPI DMA Driver updates | expand |
On Thu, Apr 27, 2023 at 12:33:13PM +0000, Joy Chakraborty wrote: > Store address width capabilities of DMA controller during init and check > the same per transfer to make sure the bits/word requirement can be met. > > Current DW DMA driver requires both tx and rx channel to be configured > and functional hence a subset of both tx and rx channel address width > capability is checked with the width requirement(n_bytes) for a > transfer. This breaks an x86 allmodconfig build: /build/stage/linux/drivers/spi/spi-dw-dma.c: In function ‘dw_spi_dma_caps_init’: /build/stage/linux/drivers/spi/spi-dw-dma.c:100:1: error: control reaches end of non-void function [-Werror=return-type] 100 | } | ^ cc1: some warnings being treated as errors
On Mon, May 8, 2023 at 6:46 PM Mark Brown <broonie@kernel.org> wrote: > > On Thu, Apr 27, 2023 at 12:33:13PM +0000, Joy Chakraborty wrote: > > Store address width capabilities of DMA controller during init and check > > the same per transfer to make sure the bits/word requirement can be met. > > > > Current DW DMA driver requires both tx and rx channel to be configured > > and functional hence a subset of both tx and rx channel address width > > capability is checked with the width requirement(n_bytes) for a > > transfer. > > This breaks an x86 allmodconfig build: > > /build/stage/linux/drivers/spi/spi-dw-dma.c: In function ‘dw_spi_dma_caps_init’: > /build/stage/linux/drivers/spi/spi-dw-dma.c:100:1: error: control reaches end of non-void function [-Werror=return-type] > 100 | } > | ^ > cc1: some warnings being treated as errors Moving "return 0" at the end of dw_spi_dma_caps_init() from patch [4/5] to patch [3/5] to solve this and sending a V10 Patch. Thanks Joy
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c index 22d0727a3789..df819652901a 100644 --- a/drivers/spi/spi-dw-dma.c +++ b/drivers/spi/spi-dw-dma.c @@ -97,6 +97,15 @@ static int dw_spi_dma_caps_init(struct dw_spi *dws) dws->dma_sg_burst = rx.max_sg_burst; else dws->dma_sg_burst = 0; + + /* + * Assuming both channels belong to the same DMA controller hence the + * peripheral side address width capabilities most likely would be + * the same. + */ + dws->dma_addr_widths = tx.dst_addr_widths & rx.src_addr_widths; + + return 0; } static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws) @@ -237,8 +246,14 @@ static bool dw_spi_can_dma(struct spi_controller *master, struct spi_device *spi, struct spi_transfer *xfer) { struct dw_spi *dws = spi_controller_get_devdata(master); + enum dma_slave_buswidth dma_bus_width; + + if (xfer->len <= dws->fifo_len) + return false; + + dma_bus_width = dw_spi_dma_convert_width(dws->n_bytes); - return xfer->len > dws->fifo_len; + return dws->dma_addr_widths & BIT(dma_bus_width); } static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed) diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 9e8eb2b52d5c..3962e6dcf880 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -190,6 +190,7 @@ struct dw_spi { struct dma_chan *rxchan; u32 rxburst; u32 dma_sg_burst; + u32 dma_addr_widths; unsigned long dma_chan_busy; dma_addr_t dma_addr; /* phy address of the Data register */ const struct dw_spi_dma_ops *dma_ops;