diff mbox

[edk2,v2,3/7] OvmfPkg: add and use industry standard macro PIIX4_PMBA_MASK

Message ID 1463498570-4469-4-git-send-email-lersek@redhat.com
State New
Headers show

Commit Message

Laszlo Ersek May 17, 2016, 3:22 p.m. UTC 
We already have the identical purpose (but different value) macro for
ICH9, namely ICH9_PMBASE_MASK in
"OvmfPkg/Include/IndustryStandard/Q35MchIch9.h".

Also, stop bit-negating signed integer constants.

Cc: Gabriel Somlo <somlo@cmu.edu>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1333238
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>

---
 OvmfPkg/Include/IndustryStandard/I440FxPiix4.h     | 2 ++
 OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c    | 2 +-
 OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c | 2 +-
 OvmfPkg/PlatformPei/Platform.c                     | 2 +-
 4 files changed, 5 insertions(+), 3 deletions(-)

-- 
1.8.3.1


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diff mbox

Patch

diff --git a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
index 8cbd685ab509..baa4c063f16a 100644
--- a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
+++ b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
@@ -28,13 +28,15 @@ 
 #define INTEL_82441_DEVICE_ID 0x1237
 
 //
 // B/D/F/Type: 0/1/3/PCI
 //
 #define POWER_MGMT_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 1, 3, (Offset))
 
 #define PIIX4_PMBA             0x40
+#define PIIX4_PMBA_MASK          (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
+                                  BIT10 | BIT9  | BIT8  | BIT7  | BIT6)
 
 #define PIIX4_PMREGMISC        0x80
 #define PIIX4_PMREGMISC_PMIOSE   BIT0
 
 #endif
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
index 109b267cf4aa..652545d8647e 100644
--- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
@@ -65,17 +65,17 @@  AcpiTimerLibConstructor (
   //
   // Check to see if the Power Management Base Address is already enabled
   //
   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
     //
     // If the Power Management Base Address is not programmed,
     // then program it now.
     //
-    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PIIX4_PMBA_VALUE);
+    PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, PIIX4_PMBA_VALUE);
 
     //
     // Enable PMBA I/O port decodes
     //
     PciOr8 (AcpiCtlReg, AcpiEnBit);
   }
 
   mAcpiTimerIoAddr = (PciRead32 (Pmba) & ~PMBA_RTE) + ACPI_TIMER_OFFSET;
diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
index c46055a09b52..735dfd2e4bf9 100644
--- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
+++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
@@ -63,17 +63,17 @@  AcpiTimerLibConstructor (
   //
   // Check to see if the Power Management Base Address is already enabled
   //
   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
     //
     // If the Power Management Base Address is not programmed,
     // then program it now.
     //
-    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PIIX4_PMBA_VALUE);
+    PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, PIIX4_PMBA_VALUE);
 
     //
     // Enable PMBA I/O port decodes
     //
     PciOr8 (AcpiCtlReg, AcpiEnBit);
   }
 
   return RETURN_SUCCESS;
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 2348b56f0b22..65b3df401abb 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -407,17 +407,17 @@  MiscInitialization (
   // has been configured (e.g., by Xen) and skip the setup here.
   // This matches the logic in AcpiTimerLibConstructor ().
   //
   if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
     //
     // The PEI phase should be exited with fully accessibe ACPI PM IO space:
     // 1. set PMBA
     //
-    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PIIX4_PMBA_VALUE);
+    PciAndThenOr32 (Pmba, ~(UINT32)PIIX4_PMBA_MASK, PIIX4_PMBA_VALUE);
 
     //
     // 2. set PCICMD/IOSE
     //
     PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
 
     //
     // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)