Message ID | 20230514122533.382910-1-mmyangfl@gmail.com |
---|---|
State | Accepted |
Commit | dc8cbdd9c68d1e840aec926bee714c38f5e315a5 |
Headers | show |
Series | arm64: dts: hi3798cv200: Fix clocks order of sd0 | expand |
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index a83b9d4f172e..ed1b5a7a6067 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -302,8 +302,8 @@ sd0: mmc@9820000 { compatible = "snps,dw-mshc"; reg = <0x9820000 0x10000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg HISTB_SDIO0_CIU_CLK>, - <&crg HISTB_SDIO0_BIU_CLK>; + clocks = <&crg HISTB_SDIO0_BIU_CLK>, + <&crg HISTB_SDIO0_CIU_CLK>; clock-names = "biu", "ciu"; resets = <&crg 0x9c 4>; reset-names = "reset";
"ciu" and "biu" were incorrectly swapped. Fix their order. Signed-off-by: David Yang <mmyangfl@gmail.com> --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)