| Message ID | 20230514054917.21318-8-quic_kriskura@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v8,1/9] dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport | expand |
On Sun, May 14, 2023 at 11:19:15AM +0530, Krishna Kurapati wrote: > Add USB and DWC3 node for tertiary port of SC8280 along with multiport > IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride > platforms. > > Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 66 ++++++++++++++++++++++++++ > 1 file changed, 66 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > index 8fa9fbfe5d00..50f6a8424537 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > @@ -3133,6 +3133,72 @@ usb_1_role_switch: endpoint { > }; > }; > > + usb_2: usb@a4f8800 { As I believe someone already pointed out, this node is not in sort order (i.e. it should go before usb@a6f8800). > + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; > + reg = <0 0x0a4f8800 0 0x400>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, > + <&gcc GCC_USB30_MP_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, > + <&gcc GCC_USB30_MP_SLEEP_CLK>, > + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, > + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, > + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, > + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, > + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; > + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", > + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; > + > + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_MP_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <200000000>; > + > + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>, > + <&pdc 126 IRQ_TYPE_EDGE_RISING>, > + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; > + > + interrupt-names = "dp_hs_phy_irq", > + "dm_hs_phy_irq", > + "ss_phy_irq", > + "pwr_event_1", > + "pwr_event_2", > + "pwr_event_3", > + "pwr_event_4"; > + > + power-domains = <&gcc USB30_MP_GDSC>; > + required-opps = <&rpmhpd_opp_nom>; > + > + resets = <&gcc GCC_USB30_MP_BCR>; > + > + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; This is not the correct interconnect master and slave; it should be MASTER_USB3_MP and SLAVE_USB3_MP. > + interconnect-names = "usb-ddr", "apps-usb"; Looks like 'wakeup-source' is missing here too. > + > + status = "disabled"; > + > + usb_2_dwc3: usb@a400000 { > + compatible = "snps,dwc3"; > + reg = <0 0x0a400000 0 0xcd00>; > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&apps_smmu 0x800 0x0>; > + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, > + <&usb_2_hsphy1>, <&usb_2_qmpphy1>, > + <&usb_2_hsphy2>, > + <&usb_2_hsphy3>; > + phy-names = "usb2-port0", "usb3-port0", > + "usb2-port1", "usb3-port1", > + "usb2-port2", > + "usb2-port3"; The phys and phy-names continuation lines above are still not aligned. > + }; > + }; > + > mdss0: display-subsystem@ae00000 { > compatible = "qcom,sc8280xp-mdss"; > reg = <0 0x0ae00000 0 0x1000>; Johan
On Mon, May 15, 2023 at 09:02:13PM +0530, Krishna Kurapati PSSNV wrote: > On 5/15/2023 7:56 PM, Johan Hovold wrote: > > On Sun, May 14, 2023 at 11:19:15AM +0530, Krishna Kurapati wrote: > >> @@ -3133,6 +3133,72 @@ usb_1_role_switch: endpoint { > >> }; > >> }; > >> > >> + usb_2: usb@a4f8800 { > > > > As I believe someone already pointed out, this node is not in sort order > > (i.e. it should go before usb@a6f8800). > I missed that message, but since I named it usb_2, so I placed it in > order after usb_1. Hope that is fine !! No, the nodes should be sorted by unit address so you need to move it. > >> + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>, > >> + <&pdc 126 IRQ_TYPE_EDGE_RISING>, > >> + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, > >> + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > >> + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, > >> + <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, > >> + <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; > >> + > >> + interrupt-names = "dp_hs_phy_irq", > >> + "dm_hs_phy_irq", > >> + "ss_phy_irq", > >> + "pwr_event_1", > >> + "pwr_event_2", > >> + "pwr_event_3", > >> + "pwr_event_4"; > >> + interconnect-names = "usb-ddr", "apps-usb"; > > > > Looks like 'wakeup-source' is missing here too. > > > > I believe this property was added to enable wakeup from system suspend > in host mode. I didn't add this property as currently I don't need to > support wakeup. If any requirement comes in future, then I might need to > add dp/dm interrupts (if any) for other ports as well and then need to > change driver code to enable/disable them on suspend/resume. If there are dp/dm/ss interrupts per ports then those need to be defined in the binding and devicetree from the start. Similar for 'wakeup-source' which indicates that the controller *can* be used to wakeup the system from suspend (which those pdc interrupts indicates). Remember that the devicetree is supposed to describe the hardware, and which features are currently supported in some version of software is mostly irrelevant. Johan
On 5/16/2023 4:24 PM, Johan Hovold wrote: > On Mon, May 15, 2023 at 09:02:13PM +0530, Krishna Kurapati PSSNV wrote: >> On 5/15/2023 7:56 PM, Johan Hovold wrote: >>> On Sun, May 14, 2023 at 11:19:15AM +0530, Krishna Kurapati wrote: > >>>> @@ -3133,6 +3133,72 @@ usb_1_role_switch: endpoint { >>>> }; >>>> }; >>>> >>>> + usb_2: usb@a4f8800 { >>> >>> As I believe someone already pointed out, this node is not in sort order >>> (i.e. it should go before usb@a6f8800). > >> I missed that message, but since I named it usb_2, so I placed it in >> order after usb_1. Hope that is fine !! > > No, the nodes should be sorted by unit address so you need to move it. > Sure, in that case will put it in between usb_0 and usb_1 nodes. >>>> + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>, >>>> + <&pdc 126 IRQ_TYPE_EDGE_RISING>, >>>> + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, >>>> + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, >>>> + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, >>>> + <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, >>>> + <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; >>>> + >>>> + interrupt-names = "dp_hs_phy_irq", >>>> + "dm_hs_phy_irq", >>>> + "ss_phy_irq", >>>> + "pwr_event_1", >>>> + "pwr_event_2", >>>> + "pwr_event_3", >>>> + "pwr_event_4"; > >>>> + interconnect-names = "usb-ddr", "apps-usb"; >>> >>> Looks like 'wakeup-source' is missing here too. >>> >> >> I believe this property was added to enable wakeup from system suspend >> in host mode. I didn't add this property as currently I don't need to >> support wakeup. If any requirement comes in future, then I might need to >> add dp/dm interrupts (if any) for other ports as well and then need to >> change driver code to enable/disable them on suspend/resume. > > If there are dp/dm/ss interrupts per ports then those need to be defined > in the binding and devicetree from the start. > > Similar for 'wakeup-source' which indicates that the controller *can* be > used to wakeup the system from suspend (which those pdc interrupts > indicates). > > Remember that the devicetree is supposed to describe the hardware, and > which features are currently supported in some version of software is > mostly irrelevant. > > Johan Can I take this up as a separate series (Wakeup support for multiport) once this series is merged. If I am adding interrupts for other ports, I can add driver code to handle those interrupts as well. Regards, Krishna,
On Tue, May 16, 2023 at 07:54:00PM +0530, Krishna Kurapati PSSNV wrote: > > > On 5/16/2023 4:24 PM, Johan Hovold wrote: > > On Mon, May 15, 2023 at 09:02:13PM +0530, Krishna Kurapati PSSNV wrote: > >> On 5/15/2023 7:56 PM, Johan Hovold wrote: > >>> On Sun, May 14, 2023 at 11:19:15AM +0530, Krishna Kurapati wrote: > > > >>>> @@ -3133,6 +3133,72 @@ usb_1_role_switch: endpoint { > >>>> }; > >>>> }; > >>>> > >>>> + usb_2: usb@a4f8800 { > >>> > >>> As I believe someone already pointed out, this node is not in sort order > >>> (i.e. it should go before usb@a6f8800). > > > >> I missed that message, but since I named it usb_2, so I placed it in > >> order after usb_1. Hope that is fine !! > > > > No, the nodes should be sorted by unit address so you need to move it. > > > > Sure, in that case will put it in between usb_0 and usb_1 nodes. No, it goes before usb_0 on sc8280xp. usb_2: usb@a4f8800 { usb_0: usb@a6f8800 { usb_1: usb@a8f8800 { > >>>> + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>, > >>>> + <&pdc 126 IRQ_TYPE_EDGE_RISING>, > >>>> + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, > >>>> + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > >>>> + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, > >>>> + <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, > >>>> + <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; > >>>> + > >>>> + interrupt-names = "dp_hs_phy_irq", > >>>> + "dm_hs_phy_irq", > >>>> + "ss_phy_irq", > >>>> + "pwr_event_1", > >>>> + "pwr_event_2", > >>>> + "pwr_event_3", > >>>> + "pwr_event_4"; > > > >>>> + interconnect-names = "usb-ddr", "apps-usb"; > >>> > >>> Looks like 'wakeup-source' is missing here too. > >>> > >> > >> I believe this property was added to enable wakeup from system suspend > >> in host mode. I didn't add this property as currently I don't need to > >> support wakeup. If any requirement comes in future, then I might need to > >> add dp/dm interrupts (if any) for other ports as well and then need to > >> change driver code to enable/disable them on suspend/resume. > > > > If there are dp/dm/ss interrupts per ports then those need to be defined > > in the binding and devicetree from the start. > > > > Similar for 'wakeup-source' which indicates that the controller *can* be > > used to wakeup the system from suspend (which those pdc interrupts > > indicates). > > > > Remember that the devicetree is supposed to describe the hardware, and > > which features are currently supported in some version of software is > > mostly irrelevant. > Can I take this up as a separate series (Wakeup support for multiport) > once this series is merged. If I am adding interrupts for other ports, I > can add driver code to handle those interrupts as well. Nope. You can possibly add driver support later, but the binding and dtsi need to be correct from the start (and it may be easier to do it all at once). Johan
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 8fa9fbfe5d00..50f6a8424537 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3133,6 +3133,72 @@ usb_1_role_switch: endpoint { }; }; + usb_2: usb@a4f8800 { + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; + reg = <0 0x0a4f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>, + <&pdc 126 IRQ_TYPE_EDGE_RISING>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq", + "pwr_event_1", + "pwr_event_2", + "pwr_event_3", + "pwr_event_4"; + + power-domains = <&gcc USB30_MP_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_MP_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + status = "disabled"; + + usb_2_dwc3: usb@a400000 { + compatible = "snps,dwc3"; + reg = <0 0x0a400000 0 0xcd00>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x800 0x0>; + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, + <&usb_2_hsphy1>, <&usb_2_qmpphy1>, + <&usb_2_hsphy2>, + <&usb_2_hsphy3>; + phy-names = "usb2-port0", "usb3-port0", + "usb2-port1", "usb3-port1", + "usb2-port2", + "usb2-port3"; + }; + }; + mdss0: display-subsystem@ae00000 { compatible = "qcom,sc8280xp-mdss"; reg = <0 0x0ae00000 0 0x1000>;
Add USB and DWC3 node for tertiary port of SC8280 along with multiport IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride platforms. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 66 ++++++++++++++++++++++++++ 1 file changed, 66 insertions(+)