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[v1,3/3] dt-bindings: arm: Adds CoreSight CSR hardware definitions

Message ID 20230526153508.6208-4-quic_jinlmao@quicinc.com
State New
Headers show
Series Add support for a streaming interface for TMC ETR | expand

Commit Message

Mao Jinlong May 26, 2023, 3:35 p.m. UTC 
Adds new coresight-csr.yaml file describing the bindings required
to define csr in the device trees.

Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
 .../bindings/arm/qcom,coresight-csr.yaml      | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml
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Patch

diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml
new file mode 100644
index 000000000000..a79b4f6a8bdf
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml
@@ -0,0 +1,62 @@ 
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/qcom,coresight-csr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CoreSight Slave Register - TPDA
+
+description: |
+  CoreSight Slave Register block hosts miscellaneous configuration registers.
+  Those configuration registers can be used to control, various coresight
+  configurations.
+
+maintainers:
+  - Mao Jinlong <quic_jinlmao@quicinc.com>
+  - Hao Zhang <quic_hazha@quicinc.com>
+
+properties:
+  $nodename:
+    pattern: "^csr(@[0-9a-f]+)$"
+  compatible:
+    items:
+      - const: qcom,coresight-csr
+
+  reg:
+    minItems: 1
+    maxItems: 2
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: apb_pclk
+
+  qcom,set-byte-cntr-support:
+    $ref: /schemas/types.yaml#/definitions/flag
+    description:
+      If set, indicates that CSR supports to set ETR_IRQ_CTRL register.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  # minimum CSR definition.
+  - |
+    csr@10001000 {
+      compatible = "qcom,coresight-csr";
+      reg = <0 0x10001000 0 0x1000>;
+
+      clocks = <&aoss_qmp>;
+      clock-names = "apb_pclk";
+      qcom,set-byte-cntr-support;
+    };
+
+...