| Message ID | 20230601042054.29075-5-quic_kathirav@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add initial support for RDP474 of IPQ5332 family | expand |
On 02/06/2023 06:05, Kathiravan T wrote: > > On 6/1/2023 10:59 PM, Krzysztof Kozlowski wrote: >> On 01/06/2023 06:20, Kathiravan T wrote: >>> Add the initial device tree support for the Reference Design >>> Platform(RDP) 474 based on IPQ5332 family of SoC. This patch carries >>> the support for Console UART, eMMC, I2C and GPIO based buttons. >>> >>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/Makefile | 1 + >>> arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts | 112 ++++++++++++++++++++ >>> 2 files changed, 113 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts >>> >>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile >>> index 4f9e81253e18..0f8c763a9bd9 100644 >>> --- a/arch/arm64/boot/dts/qcom/Makefile >>> +++ b/arch/arm64/boot/dts/qcom/Makefile >>> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb >>> +dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp474.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb >>> diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts >>> new file mode 100644 >>> index 000000000000..085729a0fdf1 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts >>> @@ -0,0 +1,112 @@ >>> +// SPDX-License-Identifier: BSD-3-Clause >>> +/* >>> + * IPQ5332 RDP474 board device tree source >>> + * >>> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. >>> + */ >>> + >>> +/dts-v1/; >>> + >>> +#include <dt-bindings/gpio/gpio.h> >>> +#include <dt-bindings/input/input.h> >>> +#include "ipq5332.dtsi" >>> + >>> +/ { >>> + model = "Qualcomm Technologies, Inc. IPQ5332 MI01.9"; >>> + compatible = "qcom,ipq5332-ap-mi01.9", "qcom,ipq5332"; >>> + >>> + aliases { >>> + serial0 = &blsp1_uart0; >>> + }; >>> + >>> + chosen { >>> + stdout-path = "serial0"; >>> + }; >>> + >>> + gpio_keys { >> No, srsly, so not only ignored the tags but also feedback? > > > Please correct me if I am wrong here.. > > This is RESEND of V1 patches (only minor correction in the subject line I sent you three emails and I assumed you got my feedback, thus it should not have been resend... > in cover letter). Also I don't see review comments as such in original > V1 as well > https://lore.kernel.org/linux-arm-msm/20230531135048.19164-1-quic_kathirav@quicinc.com/ > > Can you help to point out your review comments, I couldn't able to find out. ... but I don't see them on lore. So apparently you also did not get them. I apologize in such case. Mails are nicely sent in my outbox but apparently went to /dev/null. Original feedback: Same problems as with most of recent patches. No underscores in node names. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4f9e81253e18..0f8c763a9bd9 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp474.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts new file mode 100644 index 000000000000..085729a0fdf1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 RDP474 board device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "ipq5332.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5332 MI01.9"; + compatible = "qcom,ipq5332-ap-mi01.9", "qcom,ipq5332"; + + aliases { + serial0 = &blsp1_uart0; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + }; +}; + +&blsp1_uart0 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&blsp1_i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c_1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhc { + bus-width = <4>; + max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board { + clock-frequency = <24000000>; +}; + +/* PINCTRL */ + +&tlmm { + gpio_keys_default: gpio-keys-default-state { + pins = "gpio35"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + i2c_1_pins: i2c-1-state { + pins = "gpio29", "gpio30"; + function = "blsp1_i2c0"; + drive-strength = <8>; + bias-pull-up; + }; + + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio13"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio12"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; +};
Add the initial device tree support for the Reference Design Platform(RDP) 474 based on IPQ5332 family of SoC. This patch carries the support for Console UART, eMMC, I2C and GPIO based buttons. Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts | 112 ++++++++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts