| Message ID | 20230606-topic-qcm2290_idlestates-v2-1-580a5a2d28c9@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2] arm64: dts: qcom: qcm2290: Add CPU idle states | expand |
On Wed, Jun 07, 2023 at 01:04:19AM +0200, Konrad Dybcio wrote: > Add the (scarce) idle states for the individual CPUs, as well as the > whole cluster. This enables deeper-than-WFI cpuidle . > > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> FWIW: Reviewed-by: Stephan Gerhold <stephan@gerhold.net> > --- > Changes in v2: > - Add missing BIT(24) ("last in power level") > - Use the correct CPU low-power state (0x3 instead of 0x4) > - Link to v1: https://lore.kernel.org/r/20230606-topic-qcm2290_idlestates-v1-1-dd77eef0086e@linaro.org > --- > arch/arm64/boot/dts/qcom/qcm2290.dtsi | 61 +++++++++++++++++++++++++++++++++++ > 1 file changed, 61 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi > index b29bc4e4b837..0ed11e80e5e2 100644 > --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi > @@ -48,6 +48,8 @@ CPU0: cpu@0 { > enable-method = "psci"; > next-level-cache = <&L2_0>; > qcom,freq-domain = <&cpufreq_hw 0>; > + power-domains = <&CPU_PD0>; > + power-domain-names = "psci"; > L2_0: l2-cache { > compatible = "cache"; > cache-level = <2>; > @@ -65,6 +67,8 @@ CPU1: cpu@1 { > enable-method = "psci"; > next-level-cache = <&L2_0>; > qcom,freq-domain = <&cpufreq_hw 0>; > + power-domains = <&CPU_PD1>; > + power-domain-names = "psci"; > }; > > CPU2: cpu@2 { > @@ -77,6 +81,8 @@ CPU2: cpu@2 { > enable-method = "psci"; > next-level-cache = <&L2_0>; > qcom,freq-domain = <&cpufreq_hw 0>; > + power-domains = <&CPU_PD2>; > + power-domain-names = "psci"; > }; > > CPU3: cpu@3 { > @@ -89,6 +95,8 @@ CPU3: cpu@3 { > enable-method = "psci"; > next-level-cache = <&L2_0>; > qcom,freq-domain = <&cpufreq_hw 0>; > + power-domains = <&CPU_PD3>; > + power-domain-names = "psci"; > }; > > cpu-map { > @@ -110,6 +118,30 @@ core3 { > }; > }; > }; > + > + domain-idle-states { > + CLUSTER_SLEEP: cluster-sleep-0 { > + compatible = "domain-idle-state"; > + arm,psci-suspend-param = <0x41000043>; > + entry-latency-us = <800>; > + exit-latency-us = <2118>; > + min-residency-us = <7376>; > + }; > + }; > + > + idle-states { > + entry-method = "psci"; > + > + CPU_SLEEP: cpu-sleep-0 { > + compatible = "arm,idle-state"; > + idle-state-name = "power-collapse"; > + arm,psci-suspend-param = <0x40000003>; > + entry-latency-us = <290>; > + exit-latency-us = <376>; > + min-residency-us = <1182>; > + local-timer-stop; > + }; > + }; > }; > > firmware { > @@ -135,6 +167,35 @@ pmu { > psci { > compatible = "arm,psci-1.0"; > method = "smc"; > + > + CPU_PD0: power-domain-cpu0 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_SLEEP>; > + }; > + > + CPU_PD1: power-domain-cpu1 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_SLEEP>; > + }; > + > + CPU_PD2: power-domain-cpu2 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_SLEEP>; > + }; > + > + CPU_PD3: power-domain-cpu3 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_SLEEP>; > + }; > + > + CLUSTER_PD: power-domain-cpu-cluster { > + #power-domain-cells = <0>; > + domain-idle-states = <&CLUSTER_SLEEP>; > + }; > }; > > reserved_memory: reserved-memory { > > --- > base-commit: 6db29e14f4fb7bce9eb5290288e71b05c2b0d118 > change-id: 20230606-topic-qcm2290_idlestates-5b6062b0f4c6 > > Best regards, > -- > Konrad Dybcio <konrad.dybcio@linaro.org> >
diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index b29bc4e4b837..0ed11e80e5e2 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -48,6 +48,8 @@ CPU0: cpu@0 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -65,6 +67,8 @@ CPU1: cpu@1 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; }; CPU2: cpu@2 { @@ -77,6 +81,8 @@ CPU2: cpu@2 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; }; CPU3: cpu@3 { @@ -89,6 +95,8 @@ CPU3: cpu@3 { enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; }; cpu-map { @@ -110,6 +118,30 @@ core3 { }; }; }; + + domain-idle-states { + CLUSTER_SLEEP: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000043>; + entry-latency-us = <800>; + exit-latency-us = <2118>; + min-residency-us = <7376>; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <290>; + exit-latency-us = <376>; + min-residency-us = <1182>; + local-timer-stop; + }; + }; }; firmware { @@ -135,6 +167,35 @@ pmu { psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_SLEEP>; + }; + + CLUSTER_PD: power-domain-cpu-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP>; + }; }; reserved_memory: reserved-memory {
Add the (scarce) idle states for the individual CPUs, as well as the whole cluster. This enables deeper-than-WFI cpuidle Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- Changes in v2: - Add missing BIT(24) ("last in power level") - Use the correct CPU low-power state (0x3 instead of 0x4) - Link to v1: https://lore.kernel.org/r/20230606-topic-qcm2290_idlestates-v1-1-dd77eef0086e@linaro.org --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 61 +++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) --- base-commit: 6db29e14f4fb7bce9eb5290288e71b05c2b0d118 change-id: 20230606-topic-qcm2290_idlestates-5b6062b0f4c6 Best regards,