From patchwork Fri Feb 24 13:45:48 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 6919 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 7985523F8E for ; Fri, 24 Feb 2012 13:45:52 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 38A77A1817E for ; Fri, 24 Feb 2012 13:45:52 +0000 (UTC) Received: by iabz7 with SMTP id z7so4123028iab.11 for ; Fri, 24 Feb 2012 05:45:51 -0800 (PST) Received: from mr.google.com ([10.42.131.129]) by 10.42.131.129 with SMTP id z1mr2215473ics.53.1330091151745 (num_hops = 1); Fri, 24 Feb 2012 05:45:51 -0800 (PST) Received: by 10.42.131.129 with SMTP id z1mr1763325ics.53.1330091151692; Fri, 24 Feb 2012 05:45:51 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.11.10 with SMTP id r10cs10279ibr; Fri, 24 Feb 2012 05:45:51 -0800 (PST) Received: by 10.180.106.67 with SMTP id gs3mr4347301wib.7.1330091149922; Fri, 24 Feb 2012 05:45:49 -0800 (PST) Received: from mail-ww0-f50.google.com (mail-ww0-f50.google.com [74.125.82.50]) by mx.google.com with ESMTPS id dj2si1652137wib.17.2012.02.24.05.45.49 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 24 Feb 2012 05:45:49 -0800 (PST) Received-SPF: neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of daniel.lezcano@linaro.org) client-ip=74.125.82.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.50 is neither permitted nor denied by best guess record for domain of daniel.lezcano@linaro.org) smtp.mail=daniel.lezcano@linaro.org Received: by wgbdq11 with SMTP id dq11so2058914wgb.31 for ; Fri, 24 Feb 2012 05:45:49 -0800 (PST) Received-SPF: pass (google.com: domain of daniel.lezcano@linaro.org designates 10.180.80.40 as permitted sender) client-ip=10.180.80.40; Received: from mr.google.com ([10.180.80.40]) by 10.180.80.40 with SMTP id o8mr4671022wix.10.1330091149467 (num_hops = 1); Fri, 24 Feb 2012 05:45:49 -0800 (PST) MIME-Version: 1.0 Received: by 10.180.80.40 with SMTP id o8mr3736571wix.10.1330091149357; Fri, 24 Feb 2012 05:45:49 -0800 (PST) Received: from localhost.localdomain (AToulouse-159-1-56-228.w92-134.abo.wanadoo.fr. [92.134.87.228]) by mx.google.com with ESMTPS id hb10sm8685915wib.10.2012.02.24.05.45.47 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 24 Feb 2012 05:45:48 -0800 (PST) From: Daniel Lezcano To: linux@arm.linux.org.uk Cc: linux-arm-kernel@lists.infradead.org, patches@linaro.org, linaro-dev@lists.linaro.org, rickard.andersson@stericsson.com Subject: [PATCH] gic : check if there are pending interrupts Date: Fri, 24 Feb 2012 14:45:48 +0100 Message-Id: <1330091148-15291-1-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 1.7.5.4 X-Gm-Message-State: ALoCoQnvKqQyJeKWKh++j+nzQv8Zj6Rgf6iaX9j9yPrOwYyKyhNrS1NxyOjJNGgBjaL8jpNmvy+O The following patch checks if there are pending interrupts on the gic. This function is needed for example for the ux500 cpuidle driver. When the A9 cores and the gic are decoupled from the PRCMU, the idle routine has to check if an interrupt is pending on the gic before entering in retention mode. Signed-off-by: Daniel Lezcano --- arch/arm/common/gic.c | 37 +++++++++++++++++++++++++++++++++++ arch/arm/include/asm/hardware/gic.h | 2 +- 2 files changed, 38 insertions(+), 1 deletions(-) diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index aa52699..2528094 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -750,6 +750,43 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) } #endif +/* + * gic_pending_irq - checks if there are pending interrupts on the gic + * + * Disabling an interrupt only disables the forwarding of the + * interrupt to any CPU interface. It does not prevent the interrupt + * from changing state, for example becoming pending, or active and + * pending if it is already active. For this reason, we have to check + * the interrupt is pending *and* is enabled. + * + * Returns true if there are pending and enabled interrupts, false + * otherwise. + */ +bool gic_pending_irq(unsigned int gic_nr) +{ + u32 pr; /* Pending register */ + u32 er; /* Enable register */ + void __iomem *dist_base; + int gic_irqs; + int i; + + BUG_ON(gic_nr >= MAX_GIC_NR); + + gic_irqs = gic_data[gic_nr].gic_irqs; + dist_base = gic_data_dist_base(&gic_data[gic_nr]); + + for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { + + pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); + er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); + + if (pr & er) + return true; + } + + return false; +} + #ifdef CONFIG_OF static int gic_cnt __initdata = 0; diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 4b1ce6c..d198ac0 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h @@ -45,7 +45,7 @@ void gic_secondary_init(unsigned int); void gic_handle_irq(struct pt_regs *regs); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); - +bool gic_pending_irq(unsigned int gic_nr); static inline void gic_init(unsigned int nr, int start, void __iomem *dist , void __iomem *cpu) {