diff mbox series

[7/7] ASoC: dt-bindings: mediatek,mt79xx-afe: add audio afe document

Message ID 20230612105250.15441-8-maso.huang@mediatek.com
State New
Headers show
Series ASoC: mediatek: Add support for MT79xx SoC | expand

Commit Message

Maso Huang June 12, 2023, 10:52 a.m. UTC 
From: Maso Huang <maso.huang@mediatek.com>

Add mt79xx audio afe document.

Signed-off-by: Maso Huang <maso.huang@mediatek.com>
---
 .../bindings/sound/mediatek,mt79xx-afe.yaml   | 102 ++++++++++++++++++
 1 file changed, 102 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt79xx-afe.yaml
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt79xx-afe.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt79xx-afe.yaml
new file mode 100644
index 000000000000..11ef1cfdf49b
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/mediatek,mt79xx-afe.yaml
@@ -0,0 +1,102 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/mediatek,mt79xx-afe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek AFE PCM controller for MT79xx
+
+maintainers:
+  - Maso Huang <maso.huang@mediatek.com>
+
+properties:
+  compatible:
+    oneOf:
+      - const: mediatek,mt79xx-afe
+      - items:
+          - enum:
+              - mediatek,mt7981-afe
+              - mediatek,mt7986-afe
+              - mediatek,mt7988-afe
+          - const: mediatek,mt79xx-afe
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    minItems: 5
+    items:
+      - description: audio bus clock
+      - description: audio 26M clock
+      - description: audio intbus clock
+      - description: audio hopping clock
+      - description: audio pll clock
+      - description: mux for pcm_mck
+      - description: audio i2s/pcm mck
+
+  clock-names:
+    minItems: 5
+    items:
+      - const: aud_bus_ck
+      - const: aud_26m_ck
+      - const: aud_l_ck
+      - const: aud_aud_ck
+      - const: aud_eg2_ck
+      - const: aud_sel
+      - const: aud_i2s_m
+
+  assigned-clocks:
+    minItems: 3
+    maxItems: 4
+
+  assigned-clock-parents:
+    minItems: 3
+    maxItems: 4
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - assigned-clocks
+  - assigned-clock-parents
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/clock/mediatek,mt7981-clk.h>
+
+    afe@11210000 {
+        compatible = "mediatek,mt7981-afe","mediatek,mt79xx-afe";
+        reg = <0x11210000 0x9000>;
+        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&infracfg_ao CLK_INFRA_AUD_BUS_CK>,
+                 <&infracfg_ao CLK_INFRA_AUD_26M_CK>,
+                 <&infracfg_ao CLK_INFRA_AUD_L_CK>,
+                 <&infracfg_ao CLK_INFRA_AUD_AUD_CK>,
+                 <&infracfg_ao CLK_INFRA_AUD_EG2_CK>,
+                 <&topckgen CLK_TOP_AUD_SEL>;
+        clock-names = "aud_bus_ck",
+                      "aud_26m_ck",
+                      "aud_l_ck",
+                      "aud_aud_ck",
+                      "aud_eg2_ck",
+                      "aud_sel";
+        assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
+                          <&topckgen CLK_TOP_A1SYS_SEL>,
+                          <&topckgen CLK_TOP_AUD_L_SEL>,
+                          <&topckgen CLK_TOP_A_TUNER_SEL>;
+        assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
+                                 <&topckgen CLK_TOP_APLL2_D4>,
+                                 <&topckgen CLK_TOP_CB_APLL2_196M>,
+                                 <&topckgen CLK_TOP_APLL2_D4>;
+    };
+
+...