| Message ID | 20230704120530.1322257-1-LeoLiu-oc@zhaoxin.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v3,1/5] ACPI/APEI: Add apei_hest_parse_aer() | expand |
On Tue, Jul 04, 2023 at 08:05:30PM +0800, LeoLiu-oc wrote: > From: leoliu-oc <leoliu-oc@zhaoxin.com> > > Define Secondary Uncorrectable Error Mask Register, Secondary > Uncorrectable Error Severity Register and Secondary Error Capabilities and > Control Register bits in AER capability for PCIe to PCI/PCI-X Bridge. > Please refer to PCIe to PCI/PCI-X Bridge Specification, sec 5.2.3.2, > 5.2.3.3 and 5.2.3.4. > > Signed-off-by: leoliu-oc <leoliu-oc@zhaoxin.com> > --- > include/uapi/linux/pci_regs.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index e5f558d964939..28e20c4d0afc3 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -800,6 +800,9 @@ > #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ > #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ > #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ > +#define PCI_ERR_UNCOR_MASK2 0x30 /* PCIe to PCI/PCI-X Bridge */ > +#define PCI_ERR_UNCOR_SEVER2 0x34 /* PCIe to PCI/PCI-X Bridge */ > +#define PCI_ERR_CAP2 0x38 /* PCIe to PCI/PCI-X Bridge */ These need to line up with the offsets above, i.e., PCI_ERR_ROOT_ERR_SRC. I think these should be named: PCI_ERR_SEC_UNCOR_MASK PCI_ERR_SEC_UNCOR_SEVER PCI_ERR_SEC_ERR_CAP because "Secondary" in this context doesn't have anything to do with "2"; it just means the secondary (downstream) interface of the bridge. Bjorn
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index e5f558d964939..28e20c4d0afc3 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -800,6 +800,9 @@ #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ +#define PCI_ERR_UNCOR_MASK2 0x30 /* PCIe to PCI/PCI-X Bridge */ +#define PCI_ERR_UNCOR_SEVER2 0x34 /* PCIe to PCI/PCI-X Bridge */ +#define PCI_ERR_CAP2 0x38 /* PCIe to PCI/PCI-X Bridge */ /* Virtual Channel */ #define PCI_VC_PORT_CAP1 0x04