| Message ID | 20230711093529.18355-6-quic_devipriy@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add NSS clock controller support for IPQ9574 | expand |
On 7/11/2023 3:27 PM, Krzysztof Kozlowski wrote: > On 11/07/2023 11:35, Devi Priya wrote: >> Add a node for the nss clock controller found on ipq9574 based devices. >> >> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 44 +++++++++++++++++++++++++++ >> 1 file changed, 44 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> index f120c7c52351..257ce4a5bfd5 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -10,6 +10,8 @@ >> #include <dt-bindings/clock/qcom,ipq9574-gcc.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/reset/qcom,ipq9574-gcc.h> >> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h> >> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h> >> >> / { >> interrupt-parent = <&intc>; >> @@ -17,6 +19,30 @@ >> #size-cells = <2>; >> >> clocks { >> + bias_pll_cc_clk: bias-pll-cc-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <1200000000>; >> + #clock-cells = <0>; >> + }; >> + >> + bias_pll_nss_noc_clk: bias-pll-nss-noc-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <461500000>; >> + #clock-cells = <0>; >> + }; >> + >> + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <353000000>; >> + #clock-cells = <0>; >> + }; >> + >> + gcc_gpll0_out_aux: gcc-gpll0-out-aux { >> + compatible = "fixed-clock"; >> + clock-frequency = <800000000>; >> + #clock-cells = <0>; >> + }; > > Isn't this GCC clock? Yes, will register this in the gcc driver. Thanks, Devi Priya > >> + >> sleep_clk: sleep-clk { >> compatible = "fixed-clock"; >> #clock-cells = <0>; >> @@ -620,6 +646,24 @@ >> status = "disabled"; >> }; >> }; >> + >> + nsscc: nsscc@39b00000 { > > Node names should be generic. See also an explanation and list of > examples (not exhaustive) in DT specification: > https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation > > > Best regards, > Krzysztof >
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index f120c7c52351..257ce4a5bfd5 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -10,6 +10,8 @@ #include <dt-bindings/clock/qcom,ipq9574-gcc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/qcom,ipq9574-gcc.h> +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h> +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h> / { interrupt-parent = <&intc>; @@ -17,6 +19,30 @@ #size-cells = <2>; clocks { + bias_pll_cc_clk: bias-pll-cc-clk { + compatible = "fixed-clock"; + clock-frequency = <1200000000>; + #clock-cells = <0>; + }; + + bias_pll_nss_noc_clk: bias-pll-nss-noc-clk { + compatible = "fixed-clock"; + clock-frequency = <461500000>; + #clock-cells = <0>; + }; + + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { + compatible = "fixed-clock"; + clock-frequency = <353000000>; + #clock-cells = <0>; + }; + + gcc_gpll0_out_aux: gcc-gpll0-out-aux { + compatible = "fixed-clock"; + clock-frequency = <800000000>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -620,6 +646,24 @@ status = "disabled"; }; }; + + nsscc: nsscc@39b00000 { + compatible = "qcom,ipq9574-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&bias_pll_cc_clk>, + <&bias_pll_nss_noc_clk>, + <&bias_pll_ubi_nc_clk>, + <&gcc_gpll0_out_aux>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&xo_board_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; thermal-zones {
Add a node for the nss clock controller found on ipq9574 based devices. Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 44 +++++++++++++++++++++++++++ 1 file changed, 44 insertions(+)