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[92.17.247.99]) by smtp.gmail.com with ESMTPSA id o129sm4240934wmb.17.2016.06.17.08.14.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 17 Jun 2016 08:14:24 -0700 (PDT) From: Srinivas Kandagatla To: Andy Gross Cc: Rob Herring , David Brown , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 03/16] arm64: dts: msm8996: add blsp2_uart2 pinctrl nodes. Date: Fri, 17 Jun 2016 16:14:00 +0100 Message-Id: <1466176454-28084-4-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1466176454-28084-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1466176454-28084-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds blsp2_uart2 pinctrl nodes. Signed-off-by: Srinivas Kandagatla --- arch/arm64/boot/dts/qcom/msm8996-pins.dtsi | 50 ++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi index 4d1dba7..03c1e0d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi @@ -62,4 +62,54 @@ bias-disable; }; }; + + blsp2_uart2_2pins_default: blsp2_uart2_2pins { + pinmux { + function = "blsp_uart9"; + pins = "gpio49", "gpio50"; + }; + pinconf { + pins = "gpio49", "gpio50"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_uart2_2pins_sleep: blsp2_uart2_2pins_sleep { + pinmux { + function = "gpio"; + pins = "gpio49", "gpio50"; + }; + pinconf { + pins = "gpio49", "gpio50"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart2_4pins_default: blsp2_uart2_4pins { + pinmux { + function = "blsp_uart9"; + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + }; + + pinconf { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_uart2_4pins_sleep: blsp2_uart2_4pins_sleep { + pinmux { + function = "gpio"; + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + }; + + pinconf { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; };