Message ID | 20230724214209.208699-8-mailingradian@gmail.com |
---|---|
State | Accepted |
Commit | 8cd5597a9b18b890c743f50cfc5237fc74c6b9a0 |
Headers | show |
Series | SDM670 CPU Frequency Scaling | expand |
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index a1c207c0266d..45f9633d2d2c 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1354,5 +1354,15 @@ intc: interrupt-controller@17a00000 { interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <3>; }; + + osm_l3: interconnect@17d41000 { + compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3"; + reg = <0 0x17d41000 0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; }; };
Add the interconnect node for L3 cache on SDM670. Signed-off-by: Richard Acayan <mailingradian@gmail.com> --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)